Turbo product polar coding with hard decision cleaning

ABSTRACT

An encoder for encoding source information into an encoded codeword used in a communication channel includes a data input to receive source data, a processor, and a memory to store an encoder program. The encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, and the TPC structure comprises a data block corresponding to the source data, a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, and a second parity block having a row parity block, a joint parity block and a column parity block.

FIELD OF THE INVENTION

This invention relates to a turbo product polar coding method and device with hard decision cleaning.

BACKGROUND OF THE INVENTION

It has been proved that Polar codes can asymptotically achieve channel capacity in any arbitrary binary input memoryless channels, using successive cancellation (SC) decoding. However, the error rate performance at short codeword lengths is not competitive to the other capacity-approaching codes such as low-density parity-check (LDPC) codes. Tal and Valdy invented a breakthrough U.S. Pat. No. 9,503,126B2 to improve the polar decoding performance significantly by means of SCL decoding with CRC concatenation. It was also revealed by Zhang, Liu, Pan, and Pan (in “CRC code design for list decoding of polar codes” Communications Letter 2017) that the SCL polar decoding performance highly depends on CRC polynomial, and that minimum Hamming distance of polar-CRC concatenation codes can be increased by properly designed CRC polynomial.

Product codes based on classical linear codes such as Bose, Chaudhuri, and Hocquenghem (BCH) and Hamming codes have been used to increase the minimum Hamming distance with capability of parallel encoding and decoding. The efficient Chase decoding method was proposed by Pyndiah (in “Near-optimum decoding of product codes: block turbo codes” IEEE Transactions on Communications, vol. 46, no. 8, 1998) for soft-decision (SD) iteration for product codes to achieve near maximum-likelihood performance. The turbo-like SD iteration approach used for product codes are known as turbo product codes (TPC).

SUMMARY OF THE INVENTION

The present disclosure provides a new TPC using polar constituent codes in a non-obvious manner, where irregularity due to polarization and interleaving is exploited to improve the Hamming weight distribution. Further, we provide the way to extend SCL polar decoding for Chase-like SD iterative decoding of polar TPC. With SCL Chase decoding, the TPC based on polar codes offers a significant improvement of error rate performance compared to classical TPC based on algebraic codes such as BCH codes, Hamming codes, Reed-Solomon codes, or Reed-Muller codes.

Further, some embodiments of the present disclosure provide a product coding method using polar coding which exploits the irregularity due to polarization and interleaving to improve the hamming weight distribution of the turbo polar codes. The embodiments can use soft decision polar decoding to reduce the error performance of irregular spatially coupled polar codes. The system can consist of a product code with a plurality of parity check matrices. The parity blocks may contain row parity, column parity and a joint parity matrix. The data section can contain a set of additional parity block which exploit s the irregularity of spatially coupled polar codes to obtain better error performance.

Although polar codes have good Hamming weight distribution, it is found that short-length high-rate polar codes used as constituent codes in spatially coupled polar codes have typically shorter minimum Hamming distance than BCH codes. The short minimum Hamming distance can dominate the error rate performance only in high signal-to-noise ratio (SNR) regimes. Consequently, the spatially-coupled polar codes can potentially experience higher error floor problem than other TPC.

We disclose the method to mitigate error floor by means of replacing CRC with BCH concatenation and using hard-decision (HD) cleaning after SD iterative decoding. The concatenation of BCH code provides not only error floor removal but also reduction of the required number of iterations because HD cleaning with BCH concatenation can remove most dominant error patterns of spatially-coupled polar codes. The method is particularly effective for TPC based on polar constituent codes because the Hamming weight distribution of polar codes have specific characteristics such as higher concentration in shorter Hamming distance. In addition, the BCH concatenation can also reduce the computational complexity and decoding latency further more by enhancing tolerance against a large number of irregular polarization inactivations.

Some embodiments are based on recognition that the regular polar coding construction addresses the situation where the communication channels and modulation schemes provide uniform transmission reliability for each transmitted codeword bit. This assumption was required for theoretical proof of achieving capacity and frozen bit location design. However, some situations, such as higher-order modulation, frequency-selective fading, time-varying channels, and multi-input multi-output (MIMO) channels, result in non-uniform reliability across the transmitted bits.

Some embodiments are based on another recognition that while the regular polar coding converges toward optimal coding efficiency over large (in theory infinitely large) codes, its practical error correction performance for shorter code lengths can be improved by adding more degrees of freedom.

Some embodiments are based on realization that adaptability of the regular polar codes to the variations of the parameters of the communication channel depends on the values of parameters such as a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. Those parameters are referred herein as regular parameters of the polar code.

Some embodiments are based on realization that in addition to the regular parameters, some other parameters need to be used to increase adaptability of the polar code. Such additional parameters can include one or combination of a parameter defining an irregularity of coupling values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.

These additional parameters are referred herein as irregular parameters. The polar code designed using regular and irregular parameters is referred herein as irregular polar code. A polar encoder that encodes a codeword using an irregular polar code is referred herein as irregular polar encoder.

For example, some embodiments use plurals of polar codes, whose codeword lengths are relatively short so that the SD decoding can be carried out with short latency, wherein each SD decoding propagates SD information back and forth to the other polar decoders to correct potential errors. For this turbo-like polar encoding and decoding architecture, the error correction performance is enhanced by imposing ‘irregularity’ across the polar codes, e.g., by using different code rates, different frozen bit locations, different codeword lengths, different interleaving, and different polarization kernels. In yet another embodiment, the polar encoding architecture is irregularly permuted at the intermediate stages. To reduce the complexity and improve the performance, this irregular polar code architecture is further generalized by de-activating several polarization operations sparsely. In some embodiment, the de-activating polarization operations are further generalized by having different non-binary and high-order kernels.

In some implementations, the communication channels and/or modulation schemes result in non-uniform reliability for the transmitted codeword bits, that allows for an interleaver to be employed to improve error correction performance, and requires joint design of the interleaver and polar code construction to improve error correction performance. Accordingly, an embodiment discloses a system and method for the joint design of the interleaver and polar code construction, wherein the interleaver and polar code construction are alternatingly optimized, by taking the non-uniform reliability into consideration. This method employs an interleaver scheme where the permutation performed by the interleaver is parameterized by a set of parameters that can be designed.

Accordingly, one embodiment discloses a transmitter for transmitting an encoded codeword over a communication channel. The transmitter includes a source to accept source data to be transmitted; an irregular polar encoder operated by a processor to encode the source data with a polar code to produce the encoded codeword, wherein the polar code is specified by a set of regular parameters including one or combination of a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword, wherein the polar code is further specified by a set of irregular parameters including one or combination of a parameter defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the source data using the regular and the irregular parameters of the polar code; a modulator to modulate the encoded codeword; and a front end to transmit the modulated and encoded codeword over the communication channel.

Another embodiment discloses a method for transmitting an encoded codeword over a communication channel. The method includes accepting source data to be transmitted; encoding the source data with an irregular polar code to produce the encoded codeword, wherein the irregular polar code is specified by a set of regular parameters including one or combination of a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword, wherein the polar code is further specified by a set of irregular parameters including one or combination of a parameter defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code; modulating the encoded codeword; and transmitting the modulated and encoded codeword over the communication channel.

Yet another embodiment discloses a non-transitory computer readable storage medium embodied thereon a program executable by a processor for performing a method. The method includes accepting source data; encoding the source data with an irregular polar code to produce the encoded codeword, wherein the irregular polar code is specified by a set of regular parameters including one or combination of a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword, wherein the polar code is further specified by a set of irregular parameters including one or combination of a parameter defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code; modulating the encoded codeword; and transmitting the modulated and encoded codeword over the communication channel.

Further, according to embodiments of the present disclosure, an encoder for encoding source information into an encoded codeword to be used in a communication channel, includes a data input to receive source data to be encoded; a processor; and a memory to store an encoder program executable by the processor, wherein the encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, wherein the TPC structure comprises: a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part; and a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged to cover the first parity block using the row parity block, the joint parity block and the column parity block.

Another embodiment discloses a decoder for decoding a codeword encoded from source data by an encoder. The decoder includes a codeword input to receive the codeword to be decoded; a processor to decode the codeword into the source data according to a decoder program; and a memory to store the decoder program executable by the processor, wherein the decoder program including a row soft-decision (SD) process, a column SD process and a hard-decision (HD) process makes the processor to decode the codeword having a turbo product coding (TPC) structure into the source data according to a decoding process, wherein the decoding process includes at least two-round iterations of a series of the row and column SD processes; and at least one HD process, wherein the TPC structure comprises a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part; and a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged so as to cover the first parity block by the row parity block, the joint parity block and the column parity block.

Further, another embodiment discloses a transmitter for transmitting an encoded codeword over a communication channel. The transmitter includes a source to accept source data to be transmitted; a data input to receive source data to be encoded; a processor; and a memory to store an encoder program executable by the processor, wherein the encoder program causes the processor to encode the source data into a product coding structure, wherein the product coding structure comprises a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part; a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged to cover the first parity block using the row parity block, the joint parity block and the column parity block; a modulator to modulate the encoded codeword; and a front end to transmit the modulated and encoded codeword over the communication channel.

A system and method for encoding of polar codes according to embodiments of the present disclosure can improve the performance of error corrections and also reduce the computational complexity, decoding latency, and the power consumption of a processor (hardware processor).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a function diagram of a communications system for transmissions of digital data according to some embodiments.

FIG. 2 is a schematic of an exemplar encoding employed by an encoder of the system of FIG. 1;

FIG. 3 is a block diagram of a method for a soft-decision decoding performed by the soft-decision decoder according to one embodiment;

FIG. 4 is a schematic of list decoding generating the list of candidate paths according to some embodiments;

FIG. 5 is an example of the computation of distances between the set of candidate decoded codewords and the soft-input for determining the soft-output for each bit location using principles of some embodiments;

FIGS. 6A and 6B are schematics of embedding of multiple CRC codes in the data bits of the codeword;

FIG. 7 is a block diagram of a method for soft decoding according to some embodiments;

FIG. 8 is a block diagram of a method for decoding a codeword transmitted over a channel according to one embodiment;

FIG. 9A is a schematic of an irregular polar encoder operated to encode the codeword with an irregular polar code according to some embodiments;

FIG. 9B is a schematic of determining parameters of the irregular polar code according to one embodiment;

FIG. 10A is a schematic of bit-interleaved polar-coded modulation for non-uniform channels according to some embodiments;

FIG. 10B is a block diagram of the joint optimization procedure for the interleaver and polar code construction for non-uniform channels according to some embodiments;

FIG. 11 is an illustration of an example concatenated error correcting code with a product coding structure according to some embodiments;

FIG. 12 is an illustration of an example concatenated error correcting code with a staircase coding structure according to some embodiments;

FIG. 13 is an illustration of an example concatenated error correcting code with an irregular coding structure according to some embodiments;

FIG. 14 is a block diagram of the iterative decoding procedure of concatenated error correcting codes using a soft-decoder according to some embodiments;

FIG. 15A is an illustration of an example irregular polar coding structure using multiple interleaving units between polarization stages according to some embodiments;

FIG. 15B is a block diagram of a method for designing the intermediate interleavers according to some embodiments;

FIG. 16A is an illustration of an example irregular polar coding structure having sparsely chosen inactive polarization unit according to some embodiments;

FIG. 16B is an illustration of three example irregular polar coding structures having inactive polarization unit for a code length of 4, showing impact of de-activated polarizer in upper bound of error probability according to some embodiments;

FIG. 16C is a block diagram of a method for selective inactive polarizers of the irregular polar coding structure based on a tolerance of the decoding performance according to some embodiments;

FIG. 17 is a block diagram of a system suitable for implementing different components of the receiver for performing the soft decoding according to some embodiments and/or the transmitter for encoding the codeword according to some embodiments;

FIG. 18A shows a diagram illustrating product coding structures of a BCH-TPC and a polar TPC, according to some embodiments of the present invention;

FIG. 18B shows a block diagram illustrating a decoding process according to some embodiments of the present invention;

FIG. 18C shows bit error rate (BER) performances of BCH-based TPC and polar-based TPC, according to some embodiments of the present invention;

FIG. 19A is a diagram illustrating an example of row and column constituent codes based on Polar (256, 240, 4) concatenated with CRC-1 codes and BCH codes, according to embodiments of the present invention;

FIG. 19B is diagram illustrating decoding procedures using a row SD decoder, a column SD decoder and a BCH HD decoder, according to some embodiments of the present invention;

FIG. 19C shows BER performances obtained by decoding the encoded data block of FIG. 19A according to the decoding procedure using the row SD decoder, the column SD decoder and the BCH HD decoder of FIG. 19B, according to embodiments of the present invention;

FIG. 20A shows an example of parallel encoding with pipelining for high-throughput systems according to embodiments of the present invention; and

FIG. 20B shows an example of parallel decoding with pipelining for high-throughput systems according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments of the present invention are described hereafter with reference to the figures. It would be noted that the figures are not drawn to scale elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be also noted that the figures are only intended to facilitate the description of specific embodiments of the invention. They are not intended as an exhaustive description of the invention or as a limitation on the scope of the invention. In addition, an aspect described in conjunction with a particular embodiment of the invention is not necessarily limited to that embodiment and can be practiced in any other embodiments of the invention.

FIG. 1 shows a communications system for transmissions of digital data from a transmitter 110 to a receiver 130 over a channel 120 according to some embodiments. For example, the communication channel 120 includes air medium for radio communications, copper cable for wired communications, solid-state drive for data storage transferring, and fiber cable for fiber-optic communications. During the communications, the digital data can be corrupted by noise in the channel. The transmitter 110 uses a forward-error correction (FEC) code such as a polar code 140 to realize reliable data transmissions. The receiver tries to recover the data by using a decoder 133.

At the transmitter 110, the data to be sent comes from a source 111 configured to accept the original data. The source can include a memory to store the data, an input port to receive the data, and/or a device to generate the data. For example, in one embodiment, the source includes a voice communication device transforming an input voice signal into the digital data. The input data from the source 111 are encoded by an FEC encoder 112. The encoded data are modulated by a modulator 113. In some cases, the encoded data may be referred to as codewords. The modulator 113 uses various digital modulation formats, e.g., quadrature-amplitude modulation (QAM) with and without linear transforms such as orthogonal frequency-division multiplexing (OFDM). The modulated data are transmitted into the channel via front-end circuits 114, which can include electro-optic devices for optical communications and radio-frequency devices for radio communications, for example. The front-end can also include signal pre-processing such as band-pass filter, precoding, power loading, pilot insertion, and pre-distortion.

The channel 120 distorts the transmitted signal. For example, the channel adds additive white Gaussian noise (AWGN), co-channel interference (CCI), deep fading, impulsive noise, inter-symbol interference (ISI), nonlinear interference (NLI) due to Kerr effect, and linear chromatic dispersion (CD) as well as residual hardware imperfection.

The receiver 130 first converts the channel output into electrical received signals via front-end circuits 131, which are typically complementary of the front-end 114 at the transmitter. For example, the front-end includes linear equalization, nonlinear equalization, adaptive filtering, channel estimation, carrier phase recovery, synchronization, and polarization recovery. The received signals are demodulated at a demodulator 132 to produce an initial estimate of the bits of the transmitted codeword, which are used by the decoder 133 for recovering the source data. In various embodiments, the decoder 133 is a soft-output decoder for polar codes 140. The decoded data are sent to a data sink 134. In some embodiments, the decoder 133 is a hard-decision (HD) decoder to produce values indicative of log-likelihood ratio (LLR) of the bits from the received codeword coining from the demodulator 133. In some other embodiments, the decoder 133 includes a combination of the soft-decision decoder to produce a soft output of the decoding and the hard-decision decoder to produce values indicative of LLR of the bits from the received codeword based on the soft output received from the soft decoder.

The transmitter 110 and/or the receiver 130 can be implemented using a processor operatively connected to a memory. Each of the transmitter 110 and the receiver 130 includes one or processors (not shown). For example, the memory of the receiver 130 can store some information related to one or combination of the polar coding, the soft input and the soft output of the decoder 133, results of intermediate calculations and parameters of the decoding. For example, the polar encoded codeword can be encoded using an encoding matrix formed as a Kronecker power of a lower-triangular matrix of ones. To that end, the memory of the receiver can store the encoding matrix used by the processor of the soft decoder to decode the codeword.

All the components in the transmitter 110 and the receiver 130, including the encoder 112, the modulator 113, the demodulator 132 and the decoder 133, may be implemented by hardware, one or more processors (hardware processors), computer software (program or program modules), or a combination of hardware and computer software.

FIG. 2 shows a schematic of an exemplar encoding employed by the encoder 112 for an example polar code where there are n=16 codeword bits 210, k=10 data bits 202, and n−k=6 frozen bits 201. The 10 data bits are written to the locations of the data bits 202, while the frozen bits 201 are set to fixed, known values (which can be all zeros for simplicity in practice). Thus, in this example, the vector u:=(u₀, . . . , u_(n-1)) is formed by setting the bits (u₁, u₂, u₄, u₆, u₉, u₁₀, u₁₁, u₁₂, u₁₄, u₁₅) to the values of the 10 data bits, the remaining bits (u₀, u₃, u₅, u₇, u₈, u₁₃) to fixed, known values. The data index set is I={1,2,4,6,9,10,11,12,14,15}, for this example, which along with the parameters n, k, and the fixed values of the frozen bits comprise the polar code specification 140. The schematic illustrates procedure to transform the vector u:=(u₀, . . . , u_(n-1)) into the codeword vector c:=(c₀, . . . , c_(n-1)), which involves employing the binary exclusive-or (XOR) operation 220 as shown. These operations follow a structured pattern such that the overall procedure is equivalent to the application of the formula c=uBF^(⊗m), where the matrix multiplications are carried out over the binary field (i.e., modulo-2 arithmetic), B denotes the n×n bit-reversal permutation matrix, and F^(⊗m) is the m-th Kronecker power of the matrix

${F:=\begin{bmatrix} 1 & 0 \\ 1 & 1 \end{bmatrix}},$ and m:=log₂ n is the number of polarization stages. For regular polar coding, there are

$\frac{n}{2}$ times XOR operations per stage, resulting to nm/2 operations in total. Each XOR operation is referred herein a polarization operation for convenience because this operation creates upgraded sub-channel and downgraded sub-channel like a polarizer.

FIG. 3 shows a block diagram of a method for a soft decoding performed by the soft decoder 133 according to one embodiment. The decoder 133 can include a processor operatively connected to a memory and configured for implementing the steps of the method.

The method estimates possible values of the bits of the received codeword 310 using a successive cancelation list (SCL) decoding 320 to produce a set of candidate codewords 325 and determines 330 a distance between each candidate codeword 325 and the received codeword 310 to produce a corresponding set of distances 335. The method determines 340 a likelihood 350 of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit. For example, one embodiment calculates a soft output at each bit position of the soft input based on the difference of the distance of the closest candidate with a “1” value at that position and the distance of the closest candidate with a “0” at that position.

FIG. 4 shows a schematic of SCL decoding 320 generating the list of candidate decoding paths 420 by considering multiple decoding paths in a tree structure 400 according to some embodiments. The decoding process begins with the branching 411 from the beginning empty path 410 to consider the both possibilities of the first bit, to generate the initial two candidates 421 in the list of decoding paths. The candidate path “0 . . . ” 412 is in the list 421 and corresponds to a position within the tree structure 400. For subsequent bits locations, each of the candidate decoding paths in the list is branched to condition both possibilities of the next bit. For example, the candidates in the list are branched to progress from considering the first bit location 421 to the second bit location 422, and from considering the second bit location 422 to the third bit location 423. This corresponds to the branching seen in the tree structure 400. Since the branching causes the list size to grow, this growth is limited by restricting the list of candidates to a fixed size. In the example illustrated in this figure, the list is limited to a size of three. After the second branching, one candidate path 413 is removed from the list. After the third branching, three candidate paths 414, 415, and 416 are removed from the list.

FIG. 5 shows an example of the computation of distances between the set of candidate decoded codewords 501 and the soft-input 301 for determining the soft-output for each bit location using principles of some embodiments. In this example, the list of candidate codewords 501 includes three candidates and the distance is determined as a squared distance. To that end, the squared distance of each candidate is computed 502 with respect to the soft-input 301. In different embodiments, the number of candidates and the metric for distance determination can vary.

Let (y₁, . . . , y_(n)) denote the soft-input 301, and let (c₁, . . . , c_(n)) denote a particular candidate decoded codeword. The squared distance is calculated according to squared Euclidean distance formula Σ_(i=1) ^(n)(y_(i)−(2c_(i)−1))². Note that each candidate is converted from the binary values {0,1} to {−1, +1} by the term (2c_(i)−1). The calculation process 507 of the final soft-output 508 is then performed individually over each bit location based on the list of candidate codewords 501 and their respective squared distances 503. For each bit location, the soft-output is computed from a function of the difference of squared distance of the closest candidate with a zero in that location and the squared distance of the closest candidate with a one in that location. This is given by the formula o_(i)=f(d_(i,0)−d_(i,1)), where o_(i) is the soft-output for bit location i, d_(i,0) is the squared distance of the closest candidate with a zero in location i, and d_(i,1) is the squared distance of the closest candidate with a one in location i.

For example, in one embodiment, the function includes the difference of the distances divided by a scalar, e.g., o_(i)=(d_(i,0)−d_(i,1))/4 (where in this example, the scalar is 4). For example, a soft output of a bit at a location 504 is (1.81−2.84)/4=−0.257, wherein 1.81 is the distance of the only candidate codeword with value zero at the location 504 and 2.84 is the distance of the closest candidate with values one at the location 504. For example, a soft output of a bit at a location 505 is (3.59−1.81)/4=0.445, wherein 3.59 is the distance of the only candidate codeword with value zero at the location 505 and 1.81 is the distance of the closest candidate with values one at the location 505.

In some embodiments, if all of the candidates have the same value at that bit location, such as the bit at the location 506, then this formula cannot be applied, and instead the soft-output for that location is set according to a given parameter β>0, with the output set to o_(i)=+β if all of the candidates have the value one in that location, or o_(i)=−β if all of the candidates have the value zero in that location. The above process to compute soft-decision output values from multiple candidates is called Chase processing. In one embodiment, the number of list in SCL decoding can be reduced to 1 and multiple candidates can be generated by using the most possible error patterns based on unreliable unfrozen bits known offline.

To further increase the error correction performance, some embodiments at the cost of a small reduction in coding efficiency, embed a cyclic redundancy check (CRC) in the data bits. With this change, the decoder can be modified (referred to as SCL+CRC) so that if at least one of paths corresponds to a data sequence with a valid CRC, then the most likely path with a valid CRC is instead selected for the estimate.

FIGS. 6A and 6B show schematics of embedding of at least one CRC code in the data bits of the codeword. For example, FIG. 6A shows an example where one CRC is embedded at the end of the codeword to validate the correctness of the decoding. In this example, the bits of the codeword 600 are split into a single data part 601, containing actual message data, followed by a single CRC code 602 that is computed from and verifies 603 the data part 601.

FIG. 6B shows an example using multiple CRC codes, where the first CRC is embedded in the middle of the codeword to improve performance of SLC decoding, and the second CRC at the end of the codeword. Such multiple CRC codes embedded within the codeword can be used to validate partial decoding paths. In such a manner, the CRC can assist the SCL decoder in pruning candidate codewords at intermediate steps in the decoding procedure. In addition, multiple CRC codes can prevent potential error propagation in the SCL decoding.

In the bits of the codeword 610 multiple CRC codes are embedded splitting the codeword 610 into four parts. A first data part 611 is followed by a first CRC part 612 computed from and verifies 613 the first data part 611. The second data part 614 is followed by a second CRC part 615 computed from and verifies 616 the first data part 614.

FIG. 7 shows a block diagram of a method for soft decoding according to some embodiments, where the received codeword includes a plurality of CRC codes. For example, in one embodiment the processor of the soft decoder 133 prunes the set of candidate codewords at a partial length governed by a place of inclusion of a CRC code in the received codeword when a part of a candidate codeword includes an incorrect CRC code.

For example, the method extracts 710 a CRC value from a partially decoded candidate codeword to produce a first CRC 715 and calculates 720 a CRC by applying a well-known CRC computation procedure the partially decoded candidate codeword to produce a second CRC 725.

The method compares 730 the first CRC 715 with the second CRC 725 and removes the partially decoded candidate codeword from a list of possible combinations of the decoded bits if the first CRC does not match the second CRC.

FIG. 8 is a block diagram of a method for decoding a codeword transmitted over a channel according to one embodiment. The soft-input 801 to this procedure is the noisy codeword received over the channel, which is denoted by y:=(y₀, . . . , y_(n-1)), where each y_(i) is a noisy observation of the corresponding code bit c₁. The list decoding procedure proceed sequentially over the bits from index 0 to n−1, where in each iteration 805 for bit index i∈{0, . . . , (n−1)}, the following is performed:

Branch decoding paths 802 at data bit indices:

-   -   The list of decoding paths starts with one path if the first         index is not a data bit location (i.e., 0∉ I), in which case the         single path includes the estimate of the first bit û₀ set to the         known, fixed value of u₀. Otherwise, when the first index is a         data bit location (i.e., 0∈ I), the list of decoding paths         starts with two paths, û₀=0 and û₀=1, representing the         possibility that the first bit is either 0 or 1.     -   At subsequent bit indices i>0, the existing paths are extended.         If the bit index corresponds to a data bit location (i.e., i∈I),         then each path is branched in two paths by adding û_(i)=0 and         û_(i)=1, respectively, to each branch. Otherwise, when the bit         index does not correspond to a data bit location (i.e., i ∉ I),         each path is not branched and only extended by adding û_(i) set         to the known, fixed value of u_(i)

Check CRC validity of paths if embedded 803:

-   -   If the data bits contain embedded CRC codes, then these can be         used to reject invalid partially decoded paths.     -   At bit indices i, where the data bit locations of the partial         vector (u₀, . . . , u_(i)) contains an embedded CRC code, then         the self-consistency of the partially decoded paths can be         checked. Otherwise, nothing is done at this stage.     -   Also, once a particular CRC code has been checked, it does not         need to be rechecked for later indices.     -   For each partial path (û₀, . . . , û_(i)), check that the bits         at its data bit locations are self-consist with respect to the         embedded CRC codes. The paths that are not self-consistent are         removed from the list of paths.

Cull path list 804:

-   -   To avoid handling and exponentially large (and hence         intractable) list of candidate paths, the list is culled to a         fixed list size limit L.     -   For each partial decoded path (û₀, . . . , û_(i)), a relative         statistical likelihood that this partial decoding path is         correct, P(y, û₀, . . . , û_(i-1)|û_(i)), is calculated, which         follows from the polar code structure and underlying channel         statistics.     -   Then, the L paths with the highest likelihoods are kept, while         the remaining paths are removed from the list.

Exit loop when paths complete 806:

-   -   The loop finishes after data index i=n−1 is considered, and the         procedure moves onto comparing the candidate paths to the         soft-input 807.     -   After comparing each candidate path to the soft-input 807, the         soft-output 809 are computed based on the relative quality of         the candidate paths 808.

Another embodiment uses look-up table (LUT) to propagate the reliability information across polarization stages, wherein quantized belief messages are statistically determined to minimize the required LUT memory size without incurring much performance penalty. The adaptive LUT output based on the likelihood statistics is used to refine the frozen bit location to achieve higher coding gain to compensate for the quantization loss.

In some embodiments, the calculation of bit likelihoods during decoding uses only a few quantization bits to reduce the computational complexity and memory. One embodiment uses an adaptive LUT for processing the decoding data at each polarization operation, by considering statistics of incoming and outgoing messages, not simply approximating the quantized version of likelihoods. For example, downgrading branch of polarization operator produces lower reliable messages, and thus the quantization dynamic range should be smaller than the upgrading branch of polarizers. Using different LUTs at different polarizers at the stage and bit index, the penalty of quantized decoding can be minimized.

Irregular Polar Code Construction

Some embodiments are based on recognition that the regular polar coding construction addresses the situation where the communication channels and modulation schemes provide uniform transmission reliability for each transmitted codeword bit. This assumption is required for theoretical proof of achieving capacity and frozen bit location design. However, some situations, such as higher-order modulation, frequency-selective fading, time-varying channels, and multi-input multi-output (MIMO) channels, result in non-uniform reliability across the transmitted bits. Some embodiments are based on another recognition that while the regular polar coding converges toward optimal coding efficiency over large (in theory infinitely large) codes, its practical error correction performance for shorter code lengths can be improved.

Some embodiments are based on realization that adaptability of the regular polar coding to the variations of the parameters of the communication channel depends on the values of parameters such as a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. Those parameters are referred herein as regular parameters of the polar code.

Some embodiments are based on realization that in addition to the regular parameters, some other parameters need to be used to increase adaptability of the polar code. Such additional parameters can include one or combination of a parameter defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated XOR operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.

These additional parameters are referred herein as irregular parameters. The polar code designed using regular and irregular parameters is referred herein as irregular polar code. A polar encoder that encodes a codeword using an irregular polar code is referred herein as irregular polar encoder.

FIG. 9A shows a schematic of an irregular polar encoder operated by a processor to encode the codeword with an irregular polar code 900 to produce the encoded codeword according to some embodiments. The irregular polar encoder can be included into the encoder 112 of the transmitter 110.

The irregular polar code 900 is specified by a set of regular parameters 910 including one or combination of a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The irregular polar code 900 is further specified by a set of irregular parameters 920 including one or combination of a parameter defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated XOR operations on different stages of the polar encoding. In some embodiments, the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the irregular polar code.

FIG. 9B shows a schematic of determining parameters of the irregular polar code according to one embodiment. In this embodiment, the transmitter 110 includes a channel estimator 940 configured to determine parameters of the communication channel. For example, the parameters of the communication channel include values of non-uniform reliability for transmission of bits of the encoded codeword and/or other statistics of the channel such as signal-to-noise ratio and delay profile. The parameters of the communication channel can be determined using various methods such as least-squares channel estimation based on pilots and training symbols or a blind power estimation.

In one embodiment, the transmitter 110 includes a memory to store a mapping 930 between different values of regular and/or irregular parameters to different values of the parameters of the communication channel. In such a manner, the embodiment can select a combination 935 of values of the regular parameters and/or the irregular parameters of the polar code based on the parameters of the communication channel determined by the channel estimator 940.

In some situations, the performance of polar codes depends not only decoding methods but also frozen bit locations at encoder. To facilitate the soft-decision decoding, frozen bit locations are further refined so that the polarization effect can be boosted up, by dealing with the statistics of the likelihoods during soft-decision decoding. The frozen bit location design is particularly important for high-order modulation and frequency-selective fading channels, where different coded bits are corrupted with different noise strengths, causing non-uniform bit reliabilities. The embodiment exploits the knowledge of statistics of likelihoods for selecting frozen bit locations to improve the performance of soft-decision decoding. In addition, how to map the coded bits onto which modulation bit is important for such non-uniform reliability because different mapping can degrade the polarization effect. Therefore, careful interleaving design to map the coded bits onto modulation bits is required besides the frozen bit location design. The method of the invention provides the way to jointly design the frozen bit locations and interleaving for such high-order modulation and fading channels.

FIG. 10A shows the schematic of encoder with interleaving, where polar coding 112 produces the coded bits c₀, . . . , c₁₅, which are mapped by an interleaver 1020 to different modulation bits at QAM modulator or OFDM modulator 1010, across the least-significant bit (LSB) to the most-significant bit (MSB) planes. LSB to MSB have different bit reliabilities. Besides bit significance, each modulated symbol x₀, . . . , x₃ may have different channel noise level, e.g., due to frequency-selective fading channels. The method of the invention carefully maps the important coded bits to the reliable modulation bits so that high decoding performance is realized.

FIG. 10B shows the procedure jointly optimizing the interleaver and polar code construction for non-uniform channels. This method employs an interleaver scheme where the permutation performed by the interleaver is parameterized by a set of parameters that can be tractably optimized, that is, instead of considering all possible permutations. For example, one realization of interleaving is the quadratic polynomial permutation (QPP) interleaver, which re-orders the coded bit index i to the modulation bit index as follows: Π_(Qpp)(i)=(f ₀ +f ₁ i+f ₂ i ²)mod n, where (f₀, f₁, f₂) are the interleaver parameter. Before and after the QPP interleaving, short lexicographical permutation tables can be used so that more degrees of freedom to design the interleaving for polar coding.

First, the interleaver is set to an initial permutation 1001. Then, the polar code construction is optimized for this initial interleaver permutation 1002, by selecting the data index set corresponding to the most-reliable pseudo-channels. Then, the error correction performance of polar code construction and interleaver is evaluated 1003. This evaluation could be performed empirically via simulations and/or analytically via the error bound computable from reliability of the pseudo-channels selected by the data index set. For example, at each polarization operation, the statistics of the likelihood can be traced by the Bhattacharyya parameter, the density evolution, the Gaussian approximation, or the extrinsic information transfer (EXIT) methods. In order to capture the non-uniform reliability, the method of one embodiment uses un-conventional tracing. For example, the Bhattacharyya parameter is traced as follows: Z _(i) ^(m-1) =Z _(i) ^(m) +Z _(j) ^(m) −Z _(i) ^(m) Z _(j) ^(m) ,Z _(j) ^(m-1) =Z _(i) ^(m) Z _(j) ^(m), respectively, for downgrading branch i and upgrading branch j, where Z_(i) ^(m) is the Bhattacharyya parameter at the polarization stage m for the bit index i. The Bhattacharyya parameter corresponds to upper bound of bit error rate.

In some embodiments, in order to consider soft-decision message propagation, the EXIT method traces the reliability in terms of extrinsic mutual information across decoding stages as follows: R _(i) ^(m-1)=1−J _(TB)(√{square root over ([J _(TB) ⁻¹(1−R _(i) ^(m))]²+[J _(TB) ⁻¹(1−R _(j) ^(m))]²)}), R _(j) ^(m-1) =J _(TB)(√{square root over ([J _(TB) ⁻¹(R _(i) ^(m))]²+[J _(TB) ⁻¹(R _(j) ^(m))]²)}), respectively for the downgrading branch and upgrading branch of polarization operation, where R_(i) ^(m) is the mutual information propagated from the channel output. Here, J_(TB)(.) and J_(TB) ⁻¹(.) denote the ten Brink's J-function and its inverse function, i.e.,

${J_{TB}(x)} = {1 - {\int_{- \infty}^{\infty}{\frac{1}{\sqrt{2\pi\; x}}e^{- \frac{{({t - \frac{x^{2}}{2}})}^{2}}{2x^{2}}}{\log_{2}\left( {1 + e^{t}} \right)}{{dt}.}}}}$ Once we calculate the mutual information after decoding, the error rate at i-th input bit is obtained by

${P_{i} = {\frac{1}{2}{{erfc}\left( {\frac{1}{2\sqrt{2}}{J_{TB}^{- 1}\left( R_{i}^{1} \right)}} \right)}}},$ where erfc(x) is the complementary error function. Note that the mutual information calculation at each polarization stages should take into account the non-identical LUTs for quantized soft-decision decoding. Specifically, the above J-function is modified from continues Gaussian function to discrete-input and discrete-output function, whose mutual information can be readily calculated by the corresponding transition matrix. In addition, the EXIT trace equation is modified for different decoding methods such as belief propagation decoding, where the EXIT equation is modified to consider additional feedback information from adjacent polar stages. Note that the EXIT trace equation is readily generalized for different decoding algorithms such as BP decoding by considering feedback information from the next polarization stages in addition to the previous polarization stages.

Next, a decision to continue or end the iterative optimization procedure is made 1004, based on whether the error correction performance has converged (i.e., not changing significantly with respect to previous iterations) or if a limit on the total number of iterations has been reached. If continuing, the interleaver permutation is optimized while the polar code data set index is kept fixed 1005, then the polar code data set index is again optimized while the interleaver is kept fixed 1002, then the performance of the polar code construction and interleaver is reevaluated 1003, and a decision to continue or end the iterative optimization is again made 1004. After ending these iterations, the final result is the jointly optimized interleaver and polar code construction 1006. This joint optimization of frozen bit locations and interleaving provides boosted polarization effect especially for longer codeword lengths and wireless fading channels.

In some embodiments, a plurality of polar codes is used, where each component polar code is mutually concatenated, and soft-decision decoding output are propagated back and forth across multiple polar decoders. The benefits of multiple concatenated polar codes include the capability of parallel decoding, increased error correction potential, and decreased decoding latency.

FIG. 11 illustrates an example concatenated polar code with a product coding structure. The product coding structure employs two polar codes, the first with length n₁ and k₁ data bits, and the second with length n₂ and k₂ data bits. The encoding procedure encodes k₁×k₂ data bits, arranged in rectangular data block 1101 with k₁ rows and k₂ columns. The row parity block 1102 is produced by systematically encoding each row of the data block 1101 with the second polar code, and writing the computed parity bits for each row into the corresponding row of the k₁×(n₂−k₂) row parity block 1102. The column parity block 1103 is produced by systematically encoding each column of the data block 1101 with the first polar code, and writing the computed parity bits for each column into the corresponding column of the (n₁−k₁)×k₂ column parity block 1103. The row and column parity block 1104 is produced by systematically encoding each column of the row parity block 1102 with the first polar code, and writing the computed parity bits for each column into the corresponding column of the (n₁−k₁)×(n₂−k₂) row and column parity block 1104. Altogether, the data block 1101, row parity block 1102, column parity block 1103, and row and column parity block 1104 form an n₁×n₂ codeword block, which can be serialized and transmitted over the communication channel. In some embodiments, the product polar coding is scaled to higher-dimensional coupling, e.g., 3-dimensional cube-like structure from the 2-dimensional square-like structure. In some embodiments, each component polar coding in row and column has irregularly different parameters, e.g., the frozen bit locations are non-identical to improve the performance for iterative decoding. For typical multi-dimensional product coding, the encoding and decoding may be any specific order and direction, while the order of decoding can be optimized by a scheduling optimization method based on EXIT trajectory analysis in the presence of channel non-uniformity and polar irregularity.

FIG. 12 illustrates another example of spatially coupled polar coding with a staircase coding structure. This coding scheme involves square blocks arrange in a structure that resembles a staircase. The first block in the structure 1201, numbered as “Block 0”, includes a square block of bits that are set to fixed, known values. Subsequent blocks are numbered “Block 1”, “Block 2”, and so on, with each including a data part and a parity part. For example, “Block 1” includes the “Block 1: Data” 1211 and the “Block 1: Parity” 1212. While this figure illustrates 5 blocks, this structure is straightforward to generalize to more or fewer blocks. Each square block has dimensions of n₁×n₁. For the odd numbered subsequent blocks, the data parts (e.g., 1211, 1231) have dimensions n₁×k₁ and the parity parts (e.g., 1212, 1232) have dimensions n₁×(n₁−k₁). For the even numbered subsequent blocks, the data parts (e.g., 1221, 1241) have dimensions k₁×n₁ and the parity parts (e.g., 1222, 1242) have dimensions (n₁−k₁)×n₁. This coding structure employs a component polar code that encodes n₁+k₁ data bits into a codeword of length 2n₁. For the specific example illustrated, which includes 4 subsequent blocks after the initial “Block 0”, n₁×k₁×4 bits of data are encoded by first writing them into the data parts of the subsequent blocks 1211, 1221, 1231, 1241. Then, the parity parts of the subsequent blocks 1212, 1222, 1232, 1242 are sequentially produced as follows:

Each row of the parity part of each odd numbered block 1212, 1232 is produced by systematically encoding the concatenation of the corresponding row of the previous block and the corresponding row of the data part of the same block. For example, row i of the parity part of “Block 1” 1212 is determined by the parity bits produced by the systematic encoding of row i of “Block 0” 1201 concatenated with row i of the data part of “Block 1” 1211. In another example, row i of the parity part of “Block 3” 1232 is determined by the parity bits produced by the systematic encoding of row i of “Block 2”, which in turn includes row i of the data part of “Block 2” 1221 concatenated with row i of the parity part of “Block 2” 1222, concatenated with row i of the data part of “Block 3” 1231.

Each column of the parity part of each even numbered block 1222, 1242 is produced in a similar manner, however with the procedure operating over columns instead of the rows. For example, column i of the parity part of “Block 2” 1222 is determined by the parity bits produced by the systematic encoding of column i of “Block 1”, which in turn includes column i of the data part of “Block 1” 1211 concatenated with column i of the parity part of “Block 1” 1212, concatenated with column i of the data part of “Block 2” 1221.

The overall concatenated codeword generated by the staircase encoding procedure is all of the bits in the subsequent blocks after the initial “Block 0”, which does not need to be transmitted since it is set to fixed, known values. The bits in “Block 1”, “Block 2”, and so on are serialized for transmission over the communication channel. The benefit of the staircase polar coding structure includes reduced latency compared to single polar coding having the corresponding codeword length. The soft-decision decoding can be carried out in parallel, and a few iterations over neighboring decoders are employed in a sliding window manner for low-latency data communications in this embodiment. Other examples of spatially-coupled polar coding include braided structure, convolutional structure, tail-biting, torus tail-biting, and so on. The regular parameters of each component polar coding are individually designed in an irregular manner so that the iterative soft decoding can quickly correct the potential errors.

The regular polar coding has a limited degree of freedom to design, which determines frozen bit locations. Some embodiments increase the degrees of freedom to facilitate the soft-decision decoding by having multiple polar codes with different parameters such as code lengths, code rates, and frozen bit locations.

In particular, FIG. 13 illustrates an example concatenated polar code with an irregular coding structure. This coding scheme employs a combination of polar codes with different codeword and data lengths in an irregular structure where frozen bit locations are non-identical. The data bits of the overall concatenated code are arranged in one or more rectangular blocks, which are vertically stacked and aligned along their left edge. In our illustrated example, there are two blocks of data bits 1301 and 1302, with dimensions k₁×k₂ and k₃×k₄, respectively. Then, one or more row parity blocks are horizontally appended to right of the data blocks, with each row of the row parity blocks determined by the parity bits produced by the systematic encoding of the corresponding row of data bits that it is appended to. In our illustrated example, there are two row parity blocks 1311 and 1312. In particular, the first row parity block 1311, with dimensions k₁×p₁, is produced by systematically encoding the rows of the first data block 1301 with a component polar code that encodes k₁ data bits into a codeword of length (k₂+p₁). The second row parity block 1312, with dimensions k₂×p₂, is similarly produced by systematically encoding the rows of the second data block 1301, although now using a component polar code that encodes k₂ data bits into a codeword of length (k₄+p₂). Next, column parity blocks are vertically appended to the bottom of the data bit blocks and row parity blocks, with each column of the column parity blocks determined by the parity bits produced by the systematic encoding of the corresponding column of data and parity bits to which it is appended. In our illustrated example, there are three row parity blocks 1321, 1322, and 1323. In particular, the first column parity block 1321, with dimensions p₃×k₅, is produced by systematically encoding the first k₅ columns of both data blocks 1301 and 1302 using a component polar code that encodes (k₁+k₃) data bits into a codeword of length (k₁+k₃+p₃). The second column parity block 1322, with dimensions p₄×k₆, is produced using a component polar code that encodes (k₁+k₃) data bits into a codeword of length (k₁+k₃+p₄). Note that different columns of the second column parity block 1322 overlap different parts of the two data blocks 1301 and 1302, and the two row parity blocks 1311 and 1312. Each column of the second column parity block 1322 is produced by systematically encoding the columns directly above it.

FIG. 13 illustrates only one particular example arrangement, but this general concept includes many possible irregular arrangement of data blocks, row parity blocks, and column parity blocks that employ a variety of component polar codes. For example, protograph-based polar coding structure is constructed, where parallel polar codes are mixed at each polarizers by shift operations. Another example uses ever increasing staircase structure to provide rateless capability, where only parity bits are continuously generated by component polar codes until the receiver acknowledges the decoding completion. Therefore, the irregular coding structure and application of various component polar codes with different coding parameters produces varying degrees of freedom (and hence varying degrees of error correction performance) across the overall codeword of the concatenated code, which is potentially useful for non-uniform communication channels. This overall codeword is serialized for transmission over the communications channel, and this serialization may be permuted via an interleaver before transmission over a non-uniform channel to potentially obtain error correcting performance gains.

FIG. 14 is a block diagram of the iterative decoding procedure of concatenated polar codes using soft-decision decoders applied to various component codes. The first step is to initialize the soft-inputs for the soft-decision decoder 1400 with the channel output, that is, the noisy codeword received via the communication channels. Then, the specification of the concatenated polar code construction and the decoding schedule 1401 specifies the structure of the concatenated error correcting code and which component code(s) are soft-decoded 1410 in each decoding iteration. The soft-decoding of one or more component code(s) 1410 produces soft-outputs which are used to update the soft-inputs for the next iteration, as specified by the decoding schedule 1401. Next, a decision is made whether to proceed to the next iteration or to exit the iterative decoding procedure 1411, as specified by the decoding schedule 1401. This decoding order schedule includes, e.g., sliding window for low-latency decoding, and flooding scheduling for high parallelism. If continuing decoding iterations, the procedure returns to the soft-decision decoding 1410 of one or more component code(s), which are selected as specified in the decoding schedule 1401. This process iterates until the decoding schedule 1401 indicates that it should stop, resulting in the final soft-outputs produced by the iterative decoding, from which the decoded bits are determined 1420.

For example, with a product code, as illustrated in FIG. 11, an example decoding schedule would be to alternate between soft-decoding the row component codes and the column component codes until a fixed number of iterations have elapsed. In yet another embodiment, each component polar code has additional irregularity to facilitate soft-decision decoding.

FIG. 15A shows an example of irregular polar code, having interleavers 1510 between several, e.g., each, polarization stages. Along and/or in addition to the modulation mapping interleaver 1520, this embodiment employs more interleaving units 1510 to improve the decoding performance, by carefully designing the intermediate interleavers, without additional penalty of computational complexity.

FIG. 15B shows a block diagram of a method for designing the intermediate interleavers, while managing the computational complexity. This procedure is similar to and uses several of the same subcomponents of the procedure for jointly optimizing the interleaver and polar code construction for non-uniform channels as illustrated in FIG. 10B. First, the interleavers are set to some initial permutations 1501. Then, the polar code construction is optimized for these initial permutations of interleaver 1502, by selecting the data index set corresponding to the most-reliable pseudo-channels. Then, the error correction performance of polar code construction and interleavers is evaluated 1503. Next, a decision to continue or end the iterative optimization procedure is made 1504, based on whether the error correction performance has converged (i.e., not changing significantly with respect to previous iterations) or if a limit on the total number of iterations has been reached. If continuing, the interleaver permutations are optimized while the polar code data set index is kept fixed 1505, then the polar code data set index is again optimized while the interleaver is kept fixed 1502, then the performance of the polar code construction and interleavers is reevaluated 1503, and a decision to continue or end the iterative optimization is again made 1504. After ending these iterations, the final result is the jointly optimized interleavers and polar code construction 1506.

Notable difference between this procedure and that illustrated by FIG. 10B is that the optimization of the interleavers 1505 handle optimizing multiple permutations rather than just one. As done in the procedure of FIG. 10B, these interleaver permutations can be parameterized to make the individual optimization of each interleaver tractable. However, a brute-force search over all combinations of the multiple interleavers can drastically raise the computation complexity. To manage the computational costs, the interleavers are instead optimized sequentially, that is, individually optimizing one of the interleavers at a time while keeping the others fixed according to an optimization schedule 1507. The optimization schedule 1507 can, for example, specify that all of the interleavers are sequentially optimized in during one execution of interleavers optimization 1505, or, as another example, that only a subset of the interleavers are sequentially optimization during one execution of the interleavers optimization 1505 while rotating this selected subset across the multiple executions of the interleavers optimization 1505 in the overall iterative code construction procedure.

FIG. 16A illustrates another example of irregular polar coding structure, where several XOR polarization units are de-activated. By carefully selecting inactive polarizers, the error correction performance can be improved and the computational complexity for encoding and decoding can be reduced. In addition, several set of inactivated polarization units enables partially parallel decoding, leading to reduced latency of decoding. The location of inactive polarizers is determined by analyzing the error bound with EXIT methods so that the error bound is minimized in a greedy fashion. Because most polarizers do not drastically degrade the decoding performance, this irregular de-activation can significantly reduce the decoding complexity by choosing more inactive polarizers.

FIG. 16B shows three examples of irregular polar coding structure for a code length of 4 to illustrate the benefits provided by de-activating polarizers. The regular polar coding 1620 has two polarization stages 1621, 1622, where each stage has two polarizer units 1623, 1624 and 1625, 1626. Each polarizer unit provides worse sub-channel and better sub-channel. For example, when the encoded four bits {c₀, c₁, c₂, c₃} have uniform reliability with a Bhattacharyya parameter of 0.5, the first polarizer 1623 in the first polarization stage 1621 provides worse bit c′₀ having Bhattacharyya parameter of 0.75 and better bit c′₁ having Bhattacharyya parameter of 0.25. Similarly, the second polarizer 1623 in the first polarization stage 1621 provides worse bit c′₂ having Bhattacharyya parameter of 0.75 and better bit c′₃ having Bhattacharyya parameter of 0.25. The first polarizer 1625 in the second polarization stage 1622 provides worse bit u₀ having Bhattacharyya parameter of 0.9375 and better bit u₂ having Bhattacharyya parameter of 0.5625.

The second polarizer 1626 in the second polarization stage 1622 provides worse bit u₁ having Bhattacharyya parameter of 0.4375 and better bit u₃ having Bhattacharyya parameter of 0.0625. For the code rate of 0.5, two best bits {u₁, u₃} having lower Bhattacharyya parameters are selected as information data, while the remaining two worse bits {u₀, u₂} having higher Bhattacharyya parameters are selected as frozen bits. This regular polar coding is expected to offer an error rate performance no better than an upper bound (UB) of 1−(1−0.4375)(1−0.0625)=0.473.

One example of irregular polar coding 1630 de-activates 1610 the third polarizer unit 1625. This inactive polarizer does not change the reliability of intermediate bits {c′₀, c′₂} for the bits {u₀, u₂}, and thus those Bhattacharyya parameters are both 0.75. However, those bits are already unreliable to be frozen bits. Therefore, the error rate performance is not affected by de-activating the polarizer unit 1630 because information bits {u₁, u₃} have the same reliability as the regular polar coding 1620. This example suggests that the embodiments employing this principle can reduce the computational complexity by de-activating non-important polarizer units without causing any performance penalty.

Another example of irregular polar coding 1640 shows more important benefit, i.e., error rate performance can be improved by reducing the complexity. This irregular polar coding 1640 de-activates 1610 the fourth polarizer unit 1626. Therefore, the reliability of bits {u₁, u₃} remains the same of intermediate bits {c′₁, c′₃} having Bhattacharyya parameter of 0.25. The resulting UB is 1−(1−0.25)(1−0.25)=0.4375, which is better than the regular polar coding 1620. This example suggests that de-activating polarizer units can not only reduce the computational complexity but also improve the error rate performance, by flattening the reliability of information bits.

The irregular polar coding with inactive polarizer units can have more degrees of freedom to design than regular polar coding; specifically, there are 2^(n log) ² ^((n)/)2 possibilities to select the locations of inactive polarizer units because there are N′=n log₂ (n)/2 polarizer units. Let D be an activation matrix of size n/2-by-log₂(n), whose (i,j)-th entry is either ‘1’ or ‘0’ representing whether the i-th polarizer unit at the j-th polarization stage is active or inactive. For example, the regular polar coding 1620 has all-ones activation matrix of

${D = \begin{bmatrix} 1 & 1 \\ 1 & 1 \end{bmatrix}},$ the irregular polar coding 1630 has

${D = \begin{bmatrix} 1 & 0 \\ 1 & 1 \end{bmatrix}},$ and the irregular polar coding 1640 has

$D = {\begin{bmatrix} 1 & 1 \\ 1 & 0 \end{bmatrix}.}$ Because the total number of possible irregular polar codes is exponentially increasing, it is not straightforward to optimize the activation matrix for long irregular polar coding. In order to design the activation matrix to achieve good irregular polar coding, a greedy list search is used in the invention.

FIG. 16C shows a block diagram of a method for selecting inactive polarizers of the irregular polar coding structure according to some embodiments. The method initializes 1601 the activation matrix to be all-ones 1602, as the regular polar coding. Next, the method de-activates 1603 the previous activation matrix, i.e., changing an element of ‘1’ to ‘0’. The de-activation is considered for all possible N′ locations 1604. Then, the error rate probability is computed for each irregular polar coding. Here, the interleaver and frozen bit locations are optimized similarly as described above, during the analysis of the UB of error rate performance. The method selects 1606 the best L′ irregular polar coding having the smallest error probability. For each selected irregular polar coding, the method further de-activates 1603 different polarizer units 1607. The procedure continues 1608 until a termination condition is met. The termination condition includes, e.g., the case when the error rate performance is minimized or the case when the error rate performance becomes worse than that of the regular polar coding to minimize the computational complexity. After the list search is finished, the irregular polar coding with optimized activation table, interleaver and frozen bit locations is produced 1609.

Note that systematic coding is possible without any modifications for those irregular polar codes by using two-times irregular polar encoding like a mirrored structure as done for regular systematic polar encoders. This procedure results in the systematic coding, where the source data symbols appear in the same location at the encoded data symbols even for sparsified irregular polar coding.

The de-activating XOR of polarizer unit is equivalent to change the polar kernel of

$F = \begin{bmatrix} 1 & 0 \\ 1 & 1 \end{bmatrix}$ to another full-rank identity kernel of

$\quad\begin{bmatrix} 1 & 0 \\ 0 & 1 \end{bmatrix}$ at the inactive location. Based on this recognition, the irregular polar coding based on sparsified inactive polarizer units is further generalized to non-binary and high-order kernels. For example, some embodiments use irregular polar coding with different full-rank non-binary kernels such as

$\begin{bmatrix} 1 & 0 \\ 2 & 3 \end{bmatrix},\begin{bmatrix} 1 & 0 \\ 0 & 2 \end{bmatrix},\begin{bmatrix} 2 & 0 \\ 1 & 1 \end{bmatrix}$ for 4-ary Galois filed (i.e., module-4 arithmetic). Those different non-binary kernels are sparsely assigned for each polarizer units to improve the error rate performance and to reduce the computational complexity.

Yet another embodiment uses irregular mixture of high-order kernels; e.g.,

$\begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 1 & 1 & 1 \end{bmatrix},\begin{bmatrix} 1 & 0 & 0 \\ 1 & 1 & 0 \\ 1 & 1 & 1 \end{bmatrix},\begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 0 & 0 & 1 \end{bmatrix},\begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 0 & 1 & 1 \end{bmatrix},$ for order-3 kernels, and

$\begin{bmatrix} 1 & 0 & 0 & 0 \\ 1 & 1 & 0 & 0 \\ 1 & 0 & 1 & 0 \\ 1 & 0 & 0 & 1 \end{bmatrix},\begin{bmatrix} 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 \\ 1 & 0 & 0 & 1 \end{bmatrix},\begin{bmatrix} 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 \\ 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 1 \end{bmatrix},\begin{bmatrix} 1 & 0 & 0 & 0 \\ 1 & 1 & 0 & 0 \\ 0 & 1 & 1 & 0 \\ 0 & 0 & 1 & 1 \end{bmatrix},$ for order-4 kernels, in an irregular fashion. High-order and non-binary kernels can be combined as well.

FIG. 17 shows a block diagram of a system suitable for implementing different components of the receiver for performing the soft decoding according to some embodiments and/or the transmitter for encoding the codeword according to some embodiments. The system 1700 can include one or combination of a sensor 1710, an inertial measurement unit (IMU) 1730, a processor 1750, a memory 1760, a transceiver 1770, and a display/screen 1780, which can be operatively coupled to other components through connections 1720. The connections 1720 can comprise buses, lines, fibers, links or combination thereof.

The transceiver 1770 can, for example, include a transmitter enabled to transmit one or more signals over one or more types of wireless communication networks and a receiver to receive one or more signals transmitted over the one or more types of wireless communication networks. The transceiver 1770 can permit communications with wireless networks based on a variety of technologies such as, but not limited to, femtocells, Wi-Fi networks or wireless local area networks (WLANs), which may be based on the IEEE 802.11 family of standards, wireless personal area networks (WPANS) such Bluetooth, near field communication (NFC), networks based on the IEEE 802.15x family of standards, and/or wireless wide area networks (WWANs) such as LTE, WiMAX, etc. The system 400 can also include one or more ports for communicating over wired networks.

In some embodiments, the processor 1750 can also receive input from IMU 1730. In other embodiments, the IMU 1730 can comprise 3-axis accelerometer(s), 3-axis gyroscope(s), and/or magnetometer(s). The IMU 1730 can provide velocity, orientation, and/or other position related information to the processor 1750. In some embodiments, the IMU 1730 can output measured information in synchronization with the capture of each image frame by the sensor 1710. In some embodiments, the output of the IMU 1730 is used in part by the processor 1750 to fuse the sensor measurements and/or to further process the fused measurements.

The system 1700 can also include a screen or display 1780 rendering images, such as color and/or depth images. In some embodiments, the display 1780 can be used to display live images captured by the sensor 1710, fused images, augmented reality (AR) images, graphical user interfaces (GUIs), and other program outputs. In some embodiments, the display 1780 can include and/or be housed with a touchscreen to permit users to input data via some combination of virtual keyboards, icons, menus, or other GUIs, user gestures and/or input devices such as styli and other writing implements. In some embodiments, the display 1780 can be implemented using a liquid crystal display (LCD) display or a light emitting diode (LED) display, such as an organic LED (OLED) display. In other embodiments, the display 1780 can be a wearable display.

Exemplary system 1700 can also be modified in various ways in a manner consistent with the disclosure, such as, by adding, combining, or omitting one or more of the functional blocks shown. For example, in some configurations, the system 1700 does not include the IMU 1730 or the sensors 1770. In some embodiments, portions of the system 1700 take the form of one or more chipsets, and/or the like.

The processor 1750 can be implemented using a combination of hardware, firmware, and software. The processor 1750 can represent one or more circuits configurable to perform at least a portion of a computing procedure or process related to sensor fusion and/or methods for further processing the fused measurements. The processor 1750 retrieves instructions and/or data from memory 1760. The processor 1750 can be implemented using one or more application specific integrated circuits (ASICs), central and/or graphical processing units (CPUs and/or GPUs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, embedded processor cores, electronic devices, other electronic units designed to perform the functions described herein, or a combination thereof.

The memory 1760 can be implemented within the processor 1750 and/or external to the processor 1750. As used herein the term “memory” refers to any type of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to any particular type of memory or number of memories, or type of physical media upon which memory is stored. In some embodiments, the memory 1760 holds program codes that facilitate the soft decoding and polar encoding.

In some embodiments, additionally or alternatively to the soft decoding, the processor 1750 can perform one or combination of the soft-decoding applications 1755. For example, the soft output of the decoding can be used for decoding concatenated ECCs, which are formed from multiple component ECCs that are combined into a higher performance code. Another example is a system employing iterative equalization and decoding, where soft-decision output from decoder is fed back to demodulator to refine the decoder input iteratively. Yet another example is acting on the decoded output, e.g., showing the output on the display 1780, storing the output in the memory 1760, transmitting the output using the transceiver 1770, and/or performing the actions based on the output and measurements of the sensor 1710.

Polar-Based Turbo Product Codes (TPC)

FIG. 18A shows a square variant of product coding (FIG. 11) of size (256, 239)², illustrating turbo product code (TPC) based on an extended BCH code (eBCH-TPC) 181 and that based on polar code (polar-TPC) 182, according to some embodiments of the present invention.

The BCH-TPC 181 uses n=256 row-wise extended BCH codes denoted by eBCH(n, k, d) and other n=256 column-wise extended BCH codes, eBCH(256, 239, 6). Here, n=256, k=239, and d=6 denote the codeword length, information length, and minimum Hamming distance for the constituent codes. On the other hand, the polar-TPC 182 uses n=256 row-wise polar codes, denoted by Polar(256, 239, 4), and n=256 column-wise polar codes Polar(256, 239, 4). The polar-TPC 182 uses polar constituent codes instead of BCH constituent codes. Although the minimum Hamming distance of short-length high-rate polar codes can be shorter than BCH codes (i.e., d=4 vs. 6), the error rate performance can be superior to the BCH-TPC because the Hamming weight distribution of polar codes are well structured, as indicated in FIG. 18C. In order to minimize the impact of burst errors, TPC coded words are usually scrambled or interleaved before transmission. Note that row and column constituent codes can use different lengths and the TPC can be extended to higher dimensional product codes by spatially coupling.

The major benefits of TPC include the capability of parallel computation, low-power decoding per constituent codes, the exponential increase of minimum Hamming distance, and the near ML performance with SD decoding iteration. For m-dimensional TPC, the minimum Hamming distance can be exponentially increased as d^(n). The polar-TPC can resolve the main drawback of SCL polar decoding, which cannot be processed in parallel.

FIG. 18B is a flowchart indicating decoding procedures 1801, 1802 and 1824 using the decoder 133 that includes a row SD decoder 1813 and a column SD decoder 1814. The decoding procedures 1801 and 1802 are performed for the BCH-TPC 181 and the polar TPC 182, respectively. In this case, the decoding procedures 1801 and 1802 are iteratively performed by 2-rounds using the row and column SD decoders 1813 and 1814, as indicated in the figure.

Further, the BCH-TPC 181 and the polar-TPC 182 correspond to eBCH(256, 239, 6)×eBCH(256, 239, 6) and Polar(256, 239, 4)×Polar(256, 239, 4).

The decoder 133 (a TPC decoder) first performs a row-wise SD decoding using the row SD decoder 1813, and then the extrinsic information produced by Pyndiah's Chase processing are fed into the column-wise SD decoder 1814. Note that the row and column SD decoders 1813 and 1814 can be swapped in order without any performance loss. The TPC decoding procedure iterates the row and column SD decoding processes by using the decoders 1813 and 1814 for a certain number of iteration rounds. Also it should be noted that SD decoding by the decoder 1813 can use a quantized look-up table such as ternary message passing for implementation.

FIG. 18C shows bit error rate (BER) performances using the BCH-TPC 181 and the polar-TPC 182 at a codeword length of 256² bits for a code rate of 239²/256², according to some embodiments of the present invention.

The BER performance curves 1801 and 1802 are obtained by respectively decoding the BCH-TPC 181 and the polar-TPC 182 using a series of the row and the column SD decoders 1813 and 1814 for 2-round iteration.

The BER performance in binary-input additive white Gaussian noise (biAWGN) channel can be improved by increasing the number of iteration rounds. In FIG. 18C, it is shown that the BER curve 1802 of the polar-TPC 182 achieves 0.5 dB better than the BER curve 1801 of the BCH-TPC 181 for 2-round iteration.

A BER curve 1824 indicates the BER performance of the polar-TPC 182 based on the decoding with 3-iteration rounds. A BER curve 1824 indicates the BER performance of the eBCH-TPC 181 based on the decoding with 3-iteration rounds. Although the BER performance curve 1824 of 3-round iteration is still better than the BER curve 1823 of 3-round iteration of the BCH-TPC 182, the BER curve 1824 of polar-TPC 182 is suffered by higher error floor below a BER of 10⁻¹¹. This error floor issue is caused by the short minimum Hamming distance of Polar (256, 239, 4), compared to eBCH (256, 239, 6); and hence, the minimum Hamming distance of polar-TPC is 4²=16 whereas BCH-polar has 6²=36.

The minimum Hamming distance may be increased by concatenating another code such as CRC. FIG. 19A is a diagram illustrating an example of row and column constituent codes based on Polar (256, 240, 4) concatenated with CRC-1 codes 1901 and BCH codes 1902, according to embodiments of the present invention. In some cases, the codes 1901 and 1902 may be referred to as the polar-TPC 1901 and the polar-TPC+BCH 1902, respectively.

Each of the polar TPCs 1901 and 1902 includes a data block 90, a first parity block 190, a row parity block, a column parity block and a joint parity block. The first parity block 190 includes a first column part 191, a first corner part 192 and a first bottom part 193. The polar code 1901 uses a CRC parity 91 as the first parity block, and the polar code 1902 uses a BCH parity 92 as the first parity block.

In other words, each of the structures of the polar TPCs 1901 and 1902 is encoded from the data source by the encoder 112 so as to include the data block 90 corresponding to the source data provided from the source 111, the first parity block 190 including the first column part 191, the first corner part 192 and the first bottom part 193 and the second parity block 195 that includes a row parity block 196, a joint parity block 197 and a column parity block 198. In this case, the first parity block 190 is arranged so as to cover a right end column of the data block 90, a right bottom corner of the data block 90 and a bottom row of the data block 90 by using the first column part 191, the first corner part 192 and the first bottom part 193. Further, the second parity block 195 is arranged to cover the first parity block 190 using the row parity block 196, the joint parity block 197 and the column parity block 198.

In some cases, the first parity block 190 may be formed of CRC parity bits. Further, the first parity block 190 may be composed of BCH parity bits. In this case, a length of the BCH parity bits is determined such that a maximum number of correctable error bits is not less than a minimum Hamming distance of polar-TPCs.

In some cases, a number of the BCH parity bits is arranged to be one bit per a row and one bit per a column, in which the maximum number of correctable error bits of BCH codes can be determined not to be larger than t=floor(p/ceil(log₂(k²))), wherein floor(.), ceil(.) and p denote floor function, a ceil function, and the number of parity bits for BCH(k², p, 2t+1).

Furthermore, the row parity block 196 is adjacent to the right end column of the data block 90 through the first column part 191, and the column parity block 198 is adjacent to the bottom row of the data block 90 through the first bottom part 193 of the first parity block 190, wherein the joint parity block 197 is orthogonally adjacent to the right bottom corner of the data block 90 through the first corner part 192 of the first parity block 190.

Tal and Vardy enhanced polar codes with CRC concatenation to improve the SCL decoding. To keep the same code rate or overhead, a few frozen bits are replaced by CRC parity bits 1901. In this case, the row and column constituent codes, being referred to as the joint parity block, are based on Polar(256, 240, 4) concatenated with CRC-1 codes. However, this enhancement can be insufficient for drastically improving the performance, because the CRC parity bit length is severely limited; i.e., only 1 bit per row or column for this case. For such a short CRC parity, we cannot increase the minimum Hamming distance of concatenated polar+CRC codes even if we consider all possible polynomials.

According to an embodiment of the present invention, an encoding-decoding procedure provides the way to resolve the error floor issue in the BER curve 1824 by using a BCH parity 92 as the first parity block 190 instead of a CRC parity 91. Even though the number of parity bits is limited to only 1 bit per row or column, there are 240²−239²=479 bits in total available for the BCH parity 1902 in the whole TPC. The concatenation of BCH(240², 239², 59) with polar-TPC (256, 240, 4)² can correct at most 29 remaining bit errors. Since the minimum Hamming distance of polar-TPC is 16, the most dominant error patterns can be successfully removed by the BCH code concatenation. The BCH parity bits can be placed in any arbitrary position in a block 90. Note that the BCH code concatenation is specifically effective for polar-TPC which has structured Hamming weight because outer BCH code, which can correct at most 29 bits, used for BCH-TPC(256, 239, 6)² having minimum Hamming distance of 36 is useless.

According to an embodiment of the present invention, the decoder 133 may include a BCH HD decoder 1815 in addition to the row and column SD decoders 1813 and 1814.

FIG. 19B shows a diagram illustrating decoding procedures using a row SD decoder 1813, a column SD decoder 1814 and a BCH HD decoder 1815, according to some embodiments of the present invention.

FIG. 19C shows BER performance curves 1921 and 1922 obtained by decoding the encoded data block 90 according to the decoding procedure using the row SD decoder 1813, the column SD decoder 1814 and the BCH HD decoder 1815, according to embodiments of the present invention. In this case, the BER performance curve 1921 is obtained by decoding the polar-TPC 1901 with 2-round iteration using the row and column SD decoders 1813 and 1814 and one time HD decoding using the BCH HD decoder 1815. Further, the BER performance curve 1922 is obtained by decoding the polar TBC 1901 with 3-round iteration using the row and column SD decoders 1813 and 1814 and one time HD decoding using the BCH HD decoder 1815.

Regarding the polar-TPC with BCH concatenation, the decoder 133 performs row and column SD decoding iterations using the row SD decoder 1813 and the column SD decoder 1814, and an HD decoding of outer BCH code is performed using an HD decoder 1815 at the end of SD decoding, to clean up remaining error patterns. This HD decoding using the BCH HD decoder 1815, which can be referred to as the BCH HD cleaning, can remove the error floor for 3-iteration BER performance, as indicated by the BER curve 1922.

In addition to the benefit of the error floor mitigation, the BCH HD cleaning can significantly improve the polar-TPC performance curve 1921 for 2-iteration decoding, compared to the performance curve 1802 of the polar-TPC without HD cleaning. Effectively, we can reduce the required number of iterations to achieve the same BER performance because HD cleaning can behave as an effectively additional iteration. More specifically, the BER curve slope of HD cleaning at 2 iterations can be similar to the curve of SD decoding at 3 iterations.

Further, a decoding method of the present invention may exploit the specific Hamming weight distribution of polar codes. The Polar(256, 240, 4) has Hamming weights of [0, 0, 0, 56, 0, 1, 0, 3009, 0, 15018, . . . ] for distances of [1, 2, 3, 4, . . . ], whereas the eBCH(256, 239, 6) has Hamming weights of [0, 0, 0, 0, 0, 5757696, 0, 624879840, . . . ]. Therefore, the polar-TPC has Hamming weights of [562, 2×56, 1] for distances of [16, 24, 36]. Because the second minimum Hamming distance of 24 is also within correctable 29 bits of outer BCH code, the BCH concatenation with HD cleaning can improve the BER performance not only for error floor mitigation but also for smaller number of iterations.

The method of invention can be used for other embodiments of polar-TPC whose constituent polar codes have different codeword length n, information length k and minimum Hamming distance d. In order to keep the benefit of error floor mitigation, the BCH parity lengths are chosen such that the maximum number of correctable error bits is not less than the minimum Hamming distance of polar-TPC. This recognition can be extended to the second minimum Hamming distance or third minimum Hamming distance. For example, in addition to improve BER performance in fewer iterations, the BCH parity lengths are also chosen such that the maximum number of correctable error bits is not less than the second minimum Hamming distance of polar-TPC to correct both the most dominant and second dominant error patterns. Specifically, the maximum number of correctable error bits of BCH codes is not larger than t=floor(p/ceil(log₂(k²))), where floor(.), ceil(.), and p denote floor function, ceil function, and the number of parity bits for BCH(k², p, 2t+1). Since the polar codes have even Hamming weights, we can choose the outer BCH codes to correct a few most dominant error patterns for polar-TPC without sacrificing overheads.

In addition to the error floor mitigation and the reduction of iteration rounds, the use of BCH codes for polar-TPC has another advantage when polar constituent codes are based on irregular polarizer pruning for computational complexity reduction. The additional increase of the minimum Hamming distance by BCH concatenation can tolerate against loss due to over-pruning. More specifically, we can prune about 55% polarizer units of polar codes (256,240,4) with CRC-1 for the polar-TPC (256,239,4)² without scarifying BER performance. Whereas, 72% deactivation of polarizer units can be pruned for polar codes (256, 240, 4) with BCH concatenation. The 72% deactivation corresponds to about 4-times lower complexity for decoding, and 7-times faster decoding by partial parallelism. In consequence, the method of the invention provides non-obvious benefits with BCH concatenation for polar-TPC; error floor mitigation, reduction of required number of iterations, and enhancing irregular pruning.

FIG. 20A shows an example of parallel and pipeline implementation of a polar-TPC encoder 2000 for high-throughput transmission according to the invention. The polar-TPC encoder 2000 includes a column encoder 2010 and a row encoder 2020. The column encoder 2010 operates k=240 polar encoders in parallel, and then n=256 polar encoders in the row encoder 2020 are processed in parallel. The column and row encoders 2010 and 2020 are operated in a pipeline manner so that the encoding throughput is kept high. The implementation of the polar-TPC encoder described above can improve the effectiveness of the encoding process of the source data and enhance the performance of the processor (hardware processor) in a transmitter, increasing the throughput of the transmitter.

FIG. 20B illustrates an example of parallel and pipeline implementation of a polar-TPC decoder 3000 for high-throughput processing. The polar-TPC decoder 3000 includes a row-wise decoder 2030 and a column-wise decoder 2040. The row-wise SCL decoder 2030 is fully parallelized for n=256 rows. The SD output of the row-wise SCL decoder 2030 is fed to the column-wise SCL decoder 2040, via Chase processing 2050. The column-wise SCL decoder 2040 is also fully parallelizable for n=256 columns. The row and column decoders 2030 and 2040 can be parallelized by pipeline processing across iterations as illustrated in the figure. The capability of parallel and pipeline implementation is a great benefit of polar-TPC for high-throughput transceivers. The implementation of the polar-TPC decoder described above can improve the effectiveness of the decoding process of codewords and enhance the performance of the processor (hardware processor) in a receiver, increasing the throughput of the receiver.

The above-described embodiments of the present invention can be implemented in any of numerous ways. For example, the embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers. Such processors may be implemented as integrated circuits, with one or more processors in an integrated circuit component. Though, a processor may be implemented using circuitry in any suitable format.

Also, the embodiments of the invention may be embodied as a method, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

Use of ordinal terms such as “first,” “second,” in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Although the invention has been described by way of examples of preferred embodiments, it is to be understood that various other adaptations and modifications can be made within the spirit and scope of the invention.

Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

Descriptions Regarding Other Features

In the field of digital communications, forward error correction (FEC) through the application of an error correcting code (ECC) is the technique of encoding messages to add redundancy in order to mitigate the uncertainty introduced by a noisy communication channel, allowing transmission errors to be reduced by a decoder. Generally, an ECC is a technique for converting a sequence of data symbols (representing a message) into a more redundant sequence of code symbols that are transmitted over a noisy channel A decoder is a system or a method for recovering an estimate of the data symbols from the noisy output of the channel.

A particular family of ECCs called polar codes was introduced by Ar

kan in 2009, which provides an explicit code construction technique for binary input channels along with a decoder that provably converges toward optimal coding efficiency (i.e., achieving the channel capacity) in the asymptotic of coding over larger blocks of data. The polar codes, as proposed by Ar

kan, encode a message, represented as a sequence of k data binary symbols (“bits”), into a sequence of n code bits, where n is a power of two in general and larger than k. Specifically, the encoding procedure first writes the k data bits into the vector u:=(u₀, . . . , u_(n-1)) at the k locations specified by a data index set I⊂{0, . . . , n−1} with cardinality |I|=k, while the remaining n−k locations are set to arbitrary, but known, fixed values.

Then, the n coded bits, denoted by the vector c:=(c₀, . . . , c_(n-1)), are determined by the formula c=uBF^(⊗m), where the matrix multiplications are carried out over the binary field (i.e., modulo-2 arithmetic), B denotes the n×n bit-reversal permutation matrix, and F^(⊗m) is the m-th Kronecker power of the matrix

${F:=\begin{bmatrix} 1 & 0 \\ 1 & 1 \end{bmatrix}},$ and m:=log₂ n is the polarization stage. A polar code is fully specified by the data index set I and the parameters n and k. Thus, the key to constructing a polar code is choosing a data index set I (equivalently, its complementary set, frozen bit location) suitable for the noisy channel.

The successive cancellation (SC) decoder provided by Ar

kan helps explaining the specifics of the polar code construction technique. The SC decoder takes as input the noisy output of the channel denoted by y:=(y₀, . . . , y_(n-1)), where each y_(i) is a noisy observation of the corresponding code bit c_(i). The SC decoder proceeds sequentially over the bits, from index 0 to n−1, where for each index i∈{0, . . . , (n−1)}, an estimate û_(i) for bit u₁ is made as follows: if i∉I (i.e., frozen bit location), then û_(i) is set to the known, fixed value of u_(i), otherwise, when i∈I, û_(i) is set to the most likely value for u_(i) given the channel outputs y and assuming that the previous estimates (û₀, . . . , û_(i-1)) are correct. Sampling these estimates at the indices i∈I gives the estimate for the data bits. Each estimate û_(i) is made with respect to the conditional distribution P(y, u₀, . . . , u_(i-1)|u_(i)), which follows from the polar code structure and underlying channel statistics, and can also be thought to represent a pseudo-channel for the bit u_(i). With the aim of maximizing the accuracy of the estimates û₁, the data index set I should be chosen to select the k most reliable pseudo-channels.

Polar codes can also be systematically encoded, which is a key property to enable their application in certain concatenated codes. The systematic encoding procedure for polar codes produces a valid codeword such that the data bits appear directly in the codeword at the locations specified by the index J, which denotes the bit-reversal permutation of the locations in I. The systematic encoding procedure writes the k data bits into a vector u at the locations in J, while the other locations are set to zero, and then applies the polar encoding procedure twice, while setting the frozen bit locations (i.e., the locations not in I) to zero on the intermediate result between the encodings. For irregular polar codes, the first encoding and the second encoding are mutually mirror-structured in opposite direction of polar stages. This procedure is equivalent to applying the formula c=ϕ_(I)(uBF^(⊗m))BF^(⊗m), where ϕ_(I)(⋅) denotes setting the bits at the locations not in I equal to zero. The codeword c that results from this procedure contains the data bits written at the locations in J, while the remaining locations not in J contain bits called the parity bits. In some situations, it may be convenient to rearrange the codeword c by a permutation that places the k data bit locations (specified by the index set J) first, followed by the n−k parity locations (specified by the complement of the index set J). With such a permutation, the encoding procedure results in the vector of k data bits appended with the n−k parity bits computed by the systematic polar encoding procedure.

Although polar codes asymptotically achieve capacity limit for infinite codeword lengths, the performance at finite codeword lengths can often be inferior to other state-of-the-art ECC codes. The code design for polar codes is conducted by selecting information index I having reliable pseudo-channels. Thus, there are limited degrees of freedom to optimize polar codes, specifically, the combination selecting k locations out of n. In addition, the computational complexity of both encoding and decoding is log-linear, i.e., n log(n), which is more expensive than linear-complexity low-density parity-check codes.

Other Features of Embodiments in FIGS. 11-17

FIG. 11 illustrates an example concatenated polar code with a product coding structure. The product coding structure employs two types of polar codes, the first with length n₁ and k₁ data bits, and the second with length n₂ and k₂ data bits. The encoding procedure encodes k₁×k₂ data bits, arranged in rectangular data block 1101 with k₁ rows and k₂ columns. The row parity block 1102 is produced by systematically encoding each row of the data block 1101 with the second polar code, and writing the computed parity bits for each row into the corresponding row of the k₁×(n₂−k₂) row parity block 1102. The column parity block 1103 is produced by systematically encoding each column of the data block 1101 with the first polar code, and writing the computed parity bits for each column into the corresponding column of the (n₁−k₁)×k₂ column parity block 1103. The row and column parity block 1104 is produced by systematically encoding each column of the row parity block 1102 with the first polar code, and writing the computed parity bits for each column into the corresponding column of the (n₁−k₁)×(n₂−k₂) row and column parity block 1104. In some cases, the row and column parity block 114 can be referred to as a joint parity block. Altogether, the data block 1101, row parity block 1102, column parity block 1103, and the row and column parity block 1104 form an n₁×n₂ codeword block, which can be serialized and transmitted over the communication channel. In some embodiments, the product polar coding is scaled to higher-dimensional coupling, e.g., 3-dimensional cube-like structure from the 2-dimensional square-like structure. In some embodiments, each component polar coding in row and column has irregularly different parameters, e.g., the frozen bit locations are non-identical to improve the performance for iterative decoding.

FIG. 12 illustrates another example of spatially coupled polar coding with a staircase coding structure. This coding scheme involves square blocks arrange in a structure that resembles a staircase. The first block in the structure 1201, numbered as “Block 0”, includes a square block of bits that are set to fixed, known values. Subsequent blocks are numbered “Block 1”, “Block 2”, and so on, with each including a data part and a parity part. For example, “Block 1” includes the “Block 1: Data” 1211 and the “Block 1: Parity” 1212. While this figure illustrates 5 blocks, this structure is straightforward to generalize to more or fewer blocks. Each square block has dimensions of n₁×n₁. For the odd numbered subsequent blocks, the data parts (e.g., 1211, 1231) have dimensions n₁×k₁ and the parity parts (e.g., 1212, 1232) have dimensions n₁×(n₁−k₁). For the even numbered subsequent blocks, the data parts (e.g., 1221, 1241) have dimensions k₁×n₁ and the parity parts (e.g., 1222, 1242) have dimensions (n₁−k₁)×n₁. This coding structure employs a component polar code that encodes n₁+k₁ data bits into a codeword of length 2n₁. For the specific example illustrated, which includes 4 subsequent blocks after the initial “Block 0”, n₁×k₁×4 bits of data are encoded by first writing them into the data parts of the subsequent blocks 1211, 1221, 1231, 1241. Then, the parity parts of the subsequent blocks 1212, 1222, 1232, 1242 are sequentially produced as follows:

Each row of the parity part of each odd numbered block 1212, 1232 is produced by systematically encoding the concatenation of the corresponding row of the previous block and the corresponding row of the data part of the same block. For example, row i of the parity part of “Block 1” 1212 is determined by the parity bits produced by the systematic encoding of row i of “Block 0” 1201 concatenated with row i of the data part of “Block 1” 1211. In another example, row i of the parity part of “Block 3” 1232 is determined by the parity bits produced by the systematic encoding of row i of “Block 2”, which in turn includes row i of the data part of “Block 2” 1221 concatenated with row i of the parity part of “Block 2” 1222, concatenated with row i of the data part of “Block 3” 1231.

Each column of the parity part of each even numbered block 1222, 1242 is produced in a similar manner, however with the procedure operating over columns instead of the rows. For example, column i of the parity part of “Block 2” 1222 is determined by the parity bits produced by the systematic encoding of column i of “Block 1”, which in turn includes column i of the data part of “Block 1” 1211 concatenated with column i of the parity part of “Block 1” 1212, concatenated with column i of the data part of “Block 2” 1221.

The overall concatenated codeword generated by the staircase encoding procedure is all of the bits in the subsequent blocks after the initial “Block 0”, which does not need to be transmitted since it is set to fixed, known values. The bits in “Block 1”, “Block 2”, and so on are serialized for transmission over the communication channel. The benefit of the staircase polar coding structure includes reduced latency compared to single polar coding having the corresponding codeword length. The soft-decision decoding can be carried out in parallel, and a few iterations over neighboring decoders are employed in a sliding window manner for low-latency data communications in this embodiment. Other examples of spatially-coupled polar coding include braided structure, convolutional structure, tail-biting, torus tail-biting, and so on. The regular parameters of each component polar coding are individually designed in an irregular manner so that the iterative soft decoding can quickly correct the potential errors.

The regular polar coding has a limited degree of freedom to design, which determines frozen bit locations. Some embodiments increase the degrees of freedom to facilitate the soft-decision decoding by having multiple polar codes with different parameters such as code lengths, code rates, and frozen bit locations.

In particular, FIG. 13 illustrates an example concatenated polar code with an irregular coding structure. This coding scheme employs a combination of polar codes with different codeword and data lengths in an irregular structure where frozen bit locations are non-identical. The data bits of the overall concatenated code are arranged in one or more rectangular blocks, which are vertically stacked and aligned along their left edge. In our illustrated example, there are two blocks of data bits 1301 and 1302, with dimensions k₁×k₂ and k₃×k₄, respectively. Then, one or more row parity blocks are horizontally appended to right of the data blocks, with each row of the row parity blocks determined by the parity bits produced by the systematic encoding of the corresponding row of data bits that it is appended to. In our illustrated example, there are two row parity blocks 1311 and 1312. In particular, the first row parity block 1311, with dimensions k₁×p₁, is produced by systematically encoding the rows of the first data block 1301 with a component polar code that encodes k₁ data bits into a codeword of length (k₂+p₁). The second row parity block 1312, with dimensions k₂×p₂, is similarly produced by systematically encoding the rows of the second data block 1301, although now using a component polar code that encodes k₂ data bits into a codeword of length (k₄+p₂). Next, column parity blocks are vertically appended to the bottom of the data bit blocks and row parity blocks, with each column of the column parity blocks determined by the parity bits produced by the systematic encoding of the corresponding column of data and parity bits to which it is appended. In our illustrated example, there are three row parity blocks 1321, 1322, and 1323. In particular, the first column parity block 1321, with dimensions p₃×k₅, is produced by systematically encoding the first k₅ columns of both data blocks 1301 and 1302 using a component polar code that encodes (k₁+k₃) data bits into a codeword of length (k₁+k₃+p₃). The second column parity block 1322, with dimensions p₄×k₆, is produced using a component polar code that encodes (k₁+k₃) data bits into a codeword of length (k₁+k₃+p₄). Note that different columns of the second column parity block 1322 overlap different parts of the two data blocks 1301 and 1302, and the two row parity blocks 1311 and 1312. Each column of the second column parity block 1322 is produced by systematically encoding the columns directly above it.

FIG. 13 illustrates only one particular example arrangement, but this general concept includes many possible irregular arrangement of data blocks, row parity blocks, and column parity blocks that employ a variety of component polar codes. For example, protograph-based polar coding structure is constructed, where parallel polar codes are mixtured at each polarizers by shift operations. Another example uses ever increasing staircase structure to provide rateless capability, where only parity bits are continuously generated by component polar codes until the receiver acknowledges the decoding completion. Therefore, the irregular coding structure and application of various component polar codes with different coding parameters produces varying degrees of freedom (and hence varying degrees of error correction performance) across the overall codeword of the concatenated code, which is potentially useful for non-uniform communication channels. This overall codeword is serialized for transmission over the communications channel, and this serialization may be permuted via an interleaver before transmission over a non-uniform channel to potentially obtain error correcting performance gains.

FIG. 14 is a block diagram of the iterative decoding procedure of concatenated polar codes using soft-decision decoders applied to various component codes. The first step is to initialize the soft-inputs for the soft-decision decoder 1400 with the channel output, that is, the noisy codeword received via the communication channels. Then, the specification of the concatenated polar code construction and the decoding schedule 1401 specifies the structure of the concatenated error correcting code and which component code(s) are soft-decoded 1410 in each decoding iteration. The soft-decoding of one or more component code(s) 1410 produces soft-outputs which are used to update the soft-inputs for the next iteration, as specified by the decoding schedule 1401. Next, a decision is made whether to proceed to the next iteration or to exit the iterative decoding procedure 1411, as specified by the decoding schedule 1401. This decoding order schedule includes, e.g., sliding window for low-latency decoding, and flooding scheduling for high parallelism. If continuing decoding iterations, the procedure returns to the soft-decision decoding 1410 of one or more component code(s), which are selected as specified in the decoding schedule 1401. This process iterates until the decoding schedule 1401 indicates that it should stop, resulting in the final soft-outputs produced by the iterative decoding, from which the decoded bits are determined 1420.

For example, with a product code, as illustrated in FIG. 11, an example decoding schedule would be to alternate between soft-decoding the row component codes and the column component codes until a fixed number of iterations have elapsed. In yet another embodiment, each component polar code has additional irregularity to facilitate soft-decision decoding.

FIG. 15A shows an example of irregular polar code, having interleavers 1510 between several, e.g., each, polarization stages. Along and/or in addition to the modulation mapping interleaver 1520, this embodiment employs more interleaving units 1510 to improve the decoding performance, by carefully designing the intermediate interleavers, without additional penalty of computational complexity.

FIG. 15B shows a block diagram of a method for designing the intermediate interleavers, while managing the computational complexity. This procedure is similar to and uses several of the same subcomponents of the procedure for jointly optimizing the interleaver and polar code construction for non-uniform channels as illustrated in FIG. 10B. First, the interleavers are set to some initial permutations 1501. Then, the polar code construction is optimized for these initial permutations of interleaver 1502, by selecting the data index set corresponding to the most-reliable pseudo-channels. Then, the error correction performance of polar code construction and interleavers is evaluated 1503. Next, a decision to continue or end the iterative optimization procedure is made 1504, based on whether the error correction performance has converged (i.e., not changing significantly with respect to previous iterations) or if a limit on the total number of iterations has been reached. If continuing, the interleaver permutations are optimized while the polar code data set index is kept fixed 1505, then the polar code data set index is again optimized while the interleaver is kept fixed 1502, then the performance of the polar code construction and interleavers is reevaluated 1503, and a decision to continue or end the iterative optimization is again made 1504. After ending these iterations, the final result is the jointly optimized interleavers and polar code construction 1506.

Notable difference between this procedure and that illustrated by FIG. 10B is that the optimization of the interleavers 1505 handle optimizing multiple permutations rather than just one. As done in the procedure of FIG. 10B, these interleaver permutations can be parameterized to make the individual optimization of each interleaver tractable. However, a brute-force search over all combinations of the multiple interleavers can drastically raise the computation complexity. To manage the computational costs, the interleavers are instead optimized sequentially, that is, individually optimizing one of the interleavers at a time while keeping the others fixed according to an optimization schedule 1507. The optimization schedule 1507 can, for example, specify that all of the interleavers are sequentially optimized in during one execution of interleavers optimization 1505, or, as another example, that only a subset of the interleavers are sequentially optimization during one execution of the interleavers optimization 1505 while rotating this selected subset across the multiple executions of the interleavers optimization 1505 in the overall iterative code construction procedure.

FIG. 16A illustrates another example of irregular polar coding structure, where several XOR polarization units are de-activated. By carefully selecting inactive polarizers, the error correction performance can be improved and the computational complexity for encoding and decoding can be reduced. The location of inactive polarizers is determined by analyzing the error bound with EXIT methods so that the error bound is minimized in a greedy fashion. Because most polarizers do not drastically degrade the decoding performance, this irregular de-activation can significantly reduce the decoding complexity by choosing more inactive polarizers.

FIG. 16B shows three examples of irregular polar coding structure for a code length of 4 to illustrate the benefits provided by de-activating polarizers. The regular polar coding 1620 has two polarization stages 1621, 1622, where each stage has two polarizer units 1623, 1624 and 1625, 1626. Each polarizer unit provides worse sub-channel and better sub-channel. For example, when the encoded four bits {c₀, c₁, c₂, c₃} have uniform reliability with a Bhattacharyya parameter of 0.5, the first polarizer 1623 in the first polarization stage 1621 provides worse bit c′₀ having Bhattacharyya parameter of 0.75 and better bit c′₁ having Bhattacharyya parameter of 0.25. Similarly, the second polarizer 1623 in the first polarization stage 1621 provides worse bit c′₂ having Bhattacharyya parameter of 0.75 and better bit c′₃ having Bhattacharyya parameter of 0.25. The first polarizer 1625 in the second polarization stage 1622 provides worse bit u₀ having Bhattacharyya parameter of 0.9375 and better bit u₂ having Bhattacharyya parameter of 0.5625.

The second polarizer 1626 in the second polarization stage 1622 provides worse bit u₁ having Bhattacharyya parameter of 0.4375 and better bit u₃ having Bhattacharyya parameter of 0.0625. For the code rate of 0.5, two best bits {u₁, u₃} having lower Bhattacharyya parameters are selected as information data, while the remaining two worse bits {u₀, u₂} having higher Bhattacharyya parameters are selected as frozen bits. This regular polar coding is expected to offer an error rate performance no better than an upper bound (UB) of 1−(1−0.4375)(1−0.0625)=0.473.

One example of irregular polar coding 1630 de-activates 1610 the third polarizer unit 1625. This inactive polarizer does not change the reliability of intermediate bits {c′₀, c′₂} for the bits {u₀, u₂}, and thus those Bhattacharyya parameters are both 0.75. However, those bits are already unreliable to be frozen bits. Therefore, the error rate performance is not affected by de-activating the polarizer unit 1630 because information bits {u₁, u₃} have the same reliability as the regular polar coding 1620. This example suggests that the embodiments employing this principle can reduce the computational complexity by de-activating non-important polarizer units without causing any performance penalty.

Brief Summary of Additional Descriptions Regarding FIG. 11 Through FIG. 17

Some embodiments are based on the realization that a list-decoding of successive cancellation (SCL) of a codeword encoded with a polar code can be modified to be used not only for hard-decision decoding, but for soft-output decoding. For example, some embodiments use an SCL decoder to produce a list of candidate codewords and compare this list of candidate codewords against the soft-input of the decoder, i.e., the noisy codeword received from the communication channels, in order to generate soft-outputs. The embodiments determine the soft-output based on results of the comparison.

For example, one embodiment determines the distance of each candidate codeword of the SCL decoding from the soft-input to the decoder and determines a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit. For example, at each bit position of the candidate codeword and/or the soft-input, the embodiment calculates a soft-output based on the difference of the distance of the closest candidate with a “1” at that location and the distance of the closest candidate with a “0” at that location. In such a manner, the embodiment determines the soft-output based on results of the entire SCL decoding, while avoiding separate iterations for determination of the soft-output of each bit of the codeword.

Optionally, some embodiments use at least one cyclic redundancy check (CRC) code embedded in the codeword to validate partial decoding paths via the CRC codes. Using the CRC embedded within the codeword, as contrasted with CRC embedding at the end of the codeword, assists the SCL decoder in pruning candidate codewords at intermediate steps in the decoding procedure. This also allows error propagations in SCL decoding.

In some implementations, when all of the candidates agree for a particular location, the magnitude of the soft-output is set to a parameter β. Additionally, or alternatively, in some implementations, the soft-output is further scaled by a parameter α.

Accordingly, one embodiment discloses a receiver for decoding an encoded codeword transmitted over a communication channel. The receiver has a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel, wherein the codeword is encoded with a polar code; and a soft decoder including a processor to produce a soft output of the decoding, wherein the processor is configured for estimating possible values of the bits of the received codeword using an SCL decoding to produce a set of candidate codewords; determining a distance between each candidate codeword and the received codeword; and determining a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

Another embodiment discloses a method for decoding an encoded codeword transmitted over a communication channel, including receiving over a communication channel a codeword including a sequence of bits modified with noise of the communication channels, wherein the codeword is encoded with a polar code; estimating possible values of the bits of the received codeword using an SCL decoding to produce a set of candidate codewords; determining a distance between each candidate codeword and the received codeword; and determining a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit. At least some steps of the method are performed using a processor.

Yet another embodiment discloses a non-transitory computer readable storage medium embodied thereon a program executable by a processor for performing a method, the method includes receiving over a communication channel a codeword including a sequence of bits modified with noise of the communication channel, wherein the codeword is encoded with a polar code; estimating possible values of the bits of the received codeword using an SCL decoding to produce a set of candidate codewords; determining a distance between each candidate codeword and the received codeword; and determining a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

Supplemental Descriptions on Additional Descriptions Regarding FIG. 1 Through FIG. 17

While the SC decoder achieves capacity in the asymptotic of large code length n, as proven by Ar

kan, its practical error correction performance for shorter code lengths n can be improved. A list-decoding improvement of the SC decoder (SCL) was proposed by Tal and Vardy in 2015. The SCL decoder proceeds similarly to the SC decoder, except that for each data bit index i∈I, the decoder branches to consider both possible estimates, û_(i)=0 and û_(i)=1, and their subsequent decoding paths. If left unchecked, this branching would double the number of paths each at i∈I, leading to 2^(k) paths, corresponding to all 2^(k) possible data bit sequences, being considered. Since handling an exponentially increasing number of paths is impractical, the list-decoding approach culls the number of paths to a fixed-size list of the most likely partial paths after the doubling of paths from the branching for each i∈I. This procedure produces a fixed-size list of full decoding paths to consider, from which the most likely full path is selected to produce the estimated data sequence.

While the ultimate objective may be to make a hard-decision for the estimate of the original data symbols, it may also be useful to have a decoder that outputs soft-decision information (“soft-outputs”) that represent estimated beliefs or likelihoods about the data symbols and/or code symbols. Soft-output decoders are useful components in the construction of more complex receivers, e.g., for decoding concatenated ECCs, which are formed from multiple component ECCs that are combined into a higher performance code. Another example is a system employing iterative equalization and decoding.

Both the SC and SCL decoders provide only hard-decision outputs for polar encoded codewords. Some methods, e.g., soft cancelation (SCAN) decoding and belief propagation (BP) decoding, provide soft-decision information for the polar encoded codewords. However, those methods require multiple iterations to generate each set of soft-outputs, and, thus, time, memory, and computational power expensive.

Features Relevant to the Present Disclosure

A transmitter for transmitting an encoded codeword over a communication channel, includes a source to accept source data to be transmitted; an irregular polar encoder operated by a processor to encode the source data with a polar code to produce the encoded codeword, wherein the polar code is specified by a set of regular parameters including one or combination of a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword, wherein the polar code is further specified by a set of irregular parameters including one or combination of a parameter defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the source data using the regular and the irregular parameters of the polar code; a modulator to modulate the encoded codeword; and

a front end to transmit the modulated and encoded codeword over the communication channel.

Further, the transmitter includes a channel estimator to determine parameters of the communication channel; a memory to store a mapping between different values of the irregular parameters to different values of the parameters of the communication channel; and wherein the processor selects a combination of values of the irregular parameters of the polar code based on the parameters of the communication channel determined by the channel estimator.

In this case, the mapping further relates different values of the regular parameters and the irregular parameters to different values of the parameters of the communication channel, and wherein the processor selects a combination of values of the regular parameters and the irregular parameters of the polar code based on the parameters of the communication channel determined by the channel estimator.

Further, the parameters of the communication channel include values of non-uniform reliability for transmission of bits of the encoded codeword.

In some cases, the set of irregular parameters includes the parameter defining the irregular spatial variation of values of at least one regular parameter of the polar code to form a coding structure of a plurality of different polar codes spatially coupled with each other.

In addition, wherein the coding structure is a product coding structure employing at least two polar codes including a first polar code with length n₁ and data bits k₁ and a second polar code with length n₂ and data bits k₂ to form a special arrangement of block including a data block, a row parity block coupled to the data block along a first direction, a column parity block coupled to the data block along a second direction perpendicular to the first direction, and a row and column parity block coupled to the data block along a third direction equidistance from the first and the second directions, wherein the irregular polar encoder encodes k₁×k₂ data bits into a data block with k₁ rows and k₂ columns, wherein the irregular polar encoder encodes each row of the data block with the second polar code to produce row parity bits and adds each row of the row parity bits into corresponding k₁×(n₂−k₂) row of the row parity block, wherein the irregular polar encoder encodes each column of the data block with the first polar code to produce column parity bits and adds each column of the column parity bits into corresponding column of the (n₁−k₁)×k₂ column parity block, wherein the irregular polar encoder encodes each column of the row parity block with the first polar code to produce row and column parity bits and adds each column of the row and column parity bits into corresponding column of the (n₁−k₁)×(n₂−k₂) row and column parity block.

In such a case, the coding structure is a staircase coding structure formed by a sequence of square blocks including a first block having a data part with dimensions n₁×k₁ and a parity part with dimension n₁×(n₁−k₁) and a second block having a data part with dimensions k₁×n₁ and a parity part with dimensions (n₁−k₁)×n₁, such that concatenation of the first block and the second block forms a step of a staircase, wherein bits of the codeword are spread across the data parts of the first and the second blocks, and wherein parity bits of the parity parts of the first and the second blocks are determined using bits of the data parts of the same block and bits of the parity part of the previous block in the sequence of square blocks.

Further, the coding structure is an irregular arrangement of rectangular data blocks, row parity blocks, and column parity blocks encoded with different values of the regular parameters of the polar code.

The transmitter further includes an interleaver arranged to permute bits of the encoded codeword and to submit the permuted encoded codeword to the modulator. In this case, the interleaver maps the bits of the encoded codeword according to reliability of the modulation bits.

Further, the interleaver and at least one parameter of the polar code is jointly optimized for non-uniform reliability of the communication channel.

Further, the set of irregular parameters includes the parameter defining the irregularity of permutation of the encoded bits with different interleavers arranged between different polarization stages.

Also, the set of irregular parameters includes the parameter defining the irregularity in selection of the de-activated exclusive-or operations by specifying locations of inactive polarizers.

The several polarizers de-activated to form an inactive polarizer is selected based on a tolerance of a decoding performance, such that the de-activation of the polarizer affects the decoding performance less than allowed by the tolerance.

The irregular polar encoder adds a plurality of cyclic redundancy check (CRC) codes at different places in the encoded codeword, wherein a CRC code added after a part of the codeword is determined using a CRC encoder applied to the part of the codeword.

The set of irregular parameters includes the parameter defining the irregularity of polarization kernels in the polar code with different full-rank non-binary kernels.

The set of irregular parameters includes the parameter defining the irregularity of polarization kernels in the polar code with different high-order kernels.

A method for transmitting an encoded codeword over a communication channel, includes accepting source data to be transmitted; encoding the source data with an irregular polar code to produce the encoded codeword, wherein the irregular polar code is specified by a set of regular parameters including one or combination of a parameter defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword, wherein the polar code is further specified by a set of irregular parameters including one or combination of a parameter defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code; modulating the encoded codeword; and transmitting the modulated and encoded codeword over the communication channel.

In this case, the method further includes selecting a combination of values of the regular and irregular parameters of the polar code based on parameters of the communication channel.

Further, a non-transitory computer readable storage medium embodied thereon a program executable by a processor for performing a method, the method includes:

-   -   accepting source data; encoding the source data with an         irregular polar code to produce the encoded codeword, wherein         the irregular polar code is specified by a set of regular         parameters including one or combination of a parameter defining         a number of data bits in the codeword, a parameter defining a         data index set specifying locations of frozen bits in the         encoded codeword, and a parameter defining a number of parity         bits in the encoded codeword, wherein the polar code is further         specified by a set of irregular parameters including one or         combination of a parameter defining an irregularity of values of         at least one regular parameter of the polar code, a parameter         defining an irregularity of permutation of the encoded bits, a         parameter defining an irregularity of polarization kernels in         the polar code, and a parameter defining an irregularity in         selection of de-activated exclusive-or operations on different         stages of the polar encoding, and wherein the irregular polar         encoder encodes the codeword using the regular and the irregular         parameters of the polar code; modulating the encoded codeword;         and transmitting the modulated and encoded codeword over the         communication channel.         Other Features Relevant to the Present Disclosure

A receiver including a polar decoder for decoding an encoded codeword transmitted over a communication channel, include a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel, wherein the codeword is encoded by at least one polar encoder with a polar code; and a soft decoder operated by a processor to produce a soft output of the decoding, wherein the processor is configured to

estimate possible values of the bits of the received codeword using a successive cancelation list (SCL) decoding to produce a set of candidate codewords;

determine a distance between each candidate codeword and a soft input to the soft decoder; and determine a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

The encoded codeword is encoded using an encoding matrix formed as a Kronecker power of a lower-triangular matrix of ones, wherein the system further comprises: a memory to store the encoding matrix, and wherein the soft decoder retrieves the encoding matrix from the memory and uses the encoding matrix to decode the codeword.

The encoded codeword is encoded using an encoding matrix formed as a Kronecker power of a lower-triangular matrix of ones, with irregular selection of de-activated exclusive-or operations and intermediate interleaving between the Kronecker powers, wherein the system further comprises:

a memory to store the encoding matrix, and wherein the soft decoder retrieves the encoding matrix from the memory and uses the encoding matrix to decode the codeword.

The SCL decodes sequentially bits of codeword, while preserving a list of possible combinations of the decoded bits, wherein for each iteration of the SCL, a number of preserved combinations is no more than a threshold, such that the size of the set of candidate codewords is no more than the threshold.

The receiver receives a modulated signal from the communication channel, wherein the modulated signal is a noisy analog signal, further comprising:

a demodulator to convert the modulated signal into the soft input to the soft decoder representing the received codeword; and a hard decoder to produce values indicative of log-likelihood ratio of the bits the received codeword based on the soft output received from the soft decoder.

The soft decoder determines the distance for each candidate codeword as a Euclidean distance between the soft input and the candidate codeword. Determining the likelihood includes calculating a value of the soft output at each bit position of the soft input based on the difference of the distance of the closest candidate with a “1” value at that position and the distance of the closest candidate with a “0” at that position, when at least some values on the bit position at all candidate codewords have different values; and otherwise selecting the value of the soft output as a predetermined constant when all values on the bit position at all candidate codewords have the same value.

The calculating further comprises multiplying the values of the soft output with a scaling parameter to produce the soft output for the corresponding bit of the codeword.

The codeword includes a plurality of components encoded with a plurality of polar codes spatially coupled each other according to a spatial pattern defining non-identical set of parameters of each polar code including one or combination of a location of frozen bits, a number of data bits, a number of parity bits, and an interleaver permutation of the encoded bits, wherein the soft decoder produces the soft output according to the spatial pattern by iterating the soft decoding over the plurality of components, such that the soft output of the decoding of one component is the soft input to the decoding of another component.

The codeword is encoded with one or combination of a plurality of different interleavers used at intermediate encoding process, and with active and inactive exclusive-or operators adjusting a computational complexity and error correction performance of the soft decoding.

The soft decoder uses an adaptive look-up-table (LUT) for determining the likelihood of the values of the bits at each polarization operation, wherein the LUT specifies downgrading and upgrading branches of polarization for each bit, and wherein the LUT rule is determined so that the output quantized message has the maximum mutual information given the input quantized messages based on probability mass function of those messages.

The received codeword includes a plurality of CRC codes, wherein the processor prunes the set of candidate codewords at a partial length governed by a place of inclusion of a CRC code in the received codeword when a part of a candidate codeword includes an incorrect CRC code.

The soft decoder is configured for extracting a CRC value from a partially decoded candidate codeword to produce a first CRC; calculating a CRC by applying a CRC function to the partially decoded candidate codeword to produce a second CRC;

comparing the first CRC with the second CRC; and removing the partially decoded candidate codeword from a list of possible combinations of the decoded bits if the first CRC does not match the second CRC.

Further, a method for decoding an encoded codeword transmitted over a communication channel, includes receiving over a communication channel a codeword including a sequence of bits modified with noise of the communication channel, wherein the codeword is encoded with at least one polar encoder;

estimating possible values of the bits of a soft input represented by the received codeword using an SCL decoding to produce a set of candidate codewords; determining a distance between each candidate codeword and the received codeword; and determining a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit, wherein at least some steps of the method are performed using a processor.

In the method, wherein the SCL decodes sequentially bits of codeword, while preserving a list of possible combinations of the decoded bits, wherein for each iteration of the SCL, a number of preserved combinations is no more than a threshold, such that the size of the set of candidate codewords is no more than the threshold.

The method, further includes receiving a modulated signal from the communication channel, wherein the modulated signal is a noisy analog signal;

converting the modulated signal into the soft input; and determining the distance for each candidate codeword as a Euclidean distance between the soft input and the corresponding candidate codeword.

In the method, wherein the determining the likelihood comprises calculating a soft output at each bit position of the soft input based on the difference of the distance of the closest candidate with a “1” value at that position and the distance of the closest candidate with a “0” at that position, when at least some values on the bit position at all candidate codewords have different values; and otherwise selecting the value of the soft output as a predetermined constant when all values on the bit position at all candidate codewords have the same value.

In the method, wherein the received codeword includes a plurality of a CRC codes, wherein the processor prunes the set of candidate codewords at a partial length governed by a place of inclusion of a CRC code in the received codeword when a part of a candidate codeword includes an incorrect CRC code.

Further, a non-transitory computer readable storage medium embodied thereon a program executable by a processor for performing a method, the method includes:

receiving over a communication channel a codeword including a sequence of bits modified with noise of the communication channel, wherein the codeword is encoded with a polar encoder; estimating possible values of the bits of a soft input represented by the received codeword using an SCL decoding to produce a set of candidate codewords; determining a distance between each candidate codeword and the received codeword; and determining a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

In the memory, wherein the method further includes calculating a soft output at each bit position of the soft input based on the difference of the distance of the closest candidate with a “1” value at that position and the distance of the closest candidate with a “0” at that position, when at least some values on the bit position at all candidate codewords have different values; and otherwise selecting the value of the soft output as a predetermined constant when all values on the bit position at all candidate codewords have the same value.

A transmitter and a receiver according to embodiments of the present invention are described below.

A transmitter for transmitting an encoded codeword over a communication channel includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce the encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel. The polar code is specified by a set of regular parameters including one or combination of parameters defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The polar code is further specified by a set of irregular parameters including one or combination of parameters defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code. The irregular polar codes are spatially coupled to configure a multi-dimensional turbo product codes, where an outer code is concatenated to correct most dominant error patterns due to the short Hamming weights, and to enable irregular over-pruning kernels for reduced complexity and latency.

Further, a receiver includes a polar decoder for decoding an encoded codeword transmitted over a communication channel. The receiver includes a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel and a soft decoder operated by a processor to produce a soft output of the decoding. The codeword is encoded by at least one polar encoder with a polar code. The processor is configured to estimate possible values of the bits of the received codeword using an SCL decoding to produce a set of candidate codewords, determine a distance between each candidate codeword and a soft input to the soft decoder via Chase processing, and determine a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit. After soft-decision iterative decoding across spatially coupled codewords, hard-decision cleaning is carried out to mitigate error floor and to reduce the number of required iterations. 

What is claimed is:
 1. An encoder for encoding source data into an encoded source data to be used in a communication channel, comprising: a data input terminal to receive the source data to be encoded; a processor; and a memory to store an encoder program executable by the processor, wherein the encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, wherein the TPC structure comprises: a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part; and a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged to cover the first parity block using the row parity block, the joint parity block and the column parity block, wherein the second parity block is composed of parity bits based on polar coding, wherein the polar coding has irregular parameters as well as regular parameters, where irregular parameters include irregular bit permutations and irregular locations of inactivated exclusive-or operation in polarizer units for reduced complexity and latency; a front end to transmit the encoded source data over the communication channel.
 2. The encoder of claim 1, wherein a length of the BCH parity bits is determined such that a maximum number of correctable error bits is not less than second minimum Hamming distance for noise tolerance.
 3. The encoder of claim 1, wherein the TPC structure is extended with additional dimensions as well as row and column directions to increase minimum Hamming distance by spatially coupling more codes.
 4. The encoder of claim 1, wherein second parity bits are generated in parallel per dimension, i.e., row or column directions, where the dimension-wise generation is processed in pipeline for high-throughput encoding.
 5. The encoder of claim 1, wherein the TPC structure is expanded to convolutional structure, where parity bits are arranged to a staircase.
 6. The encoder of claim 1, wherein the encoder program includes a column encoder and a row encoder, wherein the column encoder operates k polar encoders in parallel, and the row encoder operates n polar encoders in parallel.
 7. The encoder of claim 6, wherein the column and row encoders are operated in a pipeline manner.
 8. The encoder of claim 6, wherein k=240 for the polar encoders and n=256 for the polar encoders.
 9. A decoder for decoding the encoded source data by the encoder of claim 1, comprising: a codeword input terminal to receive the encoded source data to be decoded; a processor to decode the encoded source data into decoded source data according to a decoder program; and a memory to store the decoder program executable by the processor, wherein the decoder program including a row soft-decision (SD) process, a column SD process and a hard-decision (HD) process makes the processor to decode the encoded source data having a turbo product coding (TPC) structure into the source data according to a decoding process, wherein the decoding process includes: at least two-round iterations of a series of the row and column SD processes; and at least one HD process, wherein the TPC structure comprises: a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part; and a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged so as to cover the first parity block by the row parity block, the joint parity block and the column parity block, a data output terminal to transmit the decoded source data to a data sink.
 10. The decoder of claim 9, wherein the first parity block is composed of parity bits based on BCH coding.
 11. The decoder of claim 9, wherein the second parity block is composed of parity bits based on polar coding.
 12. The decoder of claim 9, wherein the row SD process and column SD process uses Chase processing based on list decoding.
 13. The decoder of claim 9, wherein the row SD process and column SD process are pipelined in parallel for high-throughput decoding.
 14. The decoder of claim 9, wherein the HD process uses BCH decoding.
 15. The decoder of claim 9, wherein the decoder program includes a row-wise decoder and a column-wise decoder, wherein the row-wise decoder operates n polar decoders in parallel and the column-wise decoder operates k polar decoders in parallel, wherein an output of the row-wise decoder is fed to the column-wise decoder via a Chase processing.
 16. A transmitter for transmitting an encoded source data over a communication channel, comprising: a data input to receive source data to be encoded; a processor; and a memory to store an encoder program executable by the processor, wherein the encoder program causes the processor to encode the source data into a product coding structure, wherein the product coding structure comprises: a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part; a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged to cover the first parity block using the row parity block, the joint parity block and the column parity block, wherein the second parity block is composed of parity bits based on polar coding, wherein the polar coding has irregular parameters as well as regular parameters, where irregular parameters include irregular bit permutations and irregular locations of inactivated exclusive-or operation in polarizer units for reduced complexity and latency; a modulator to modulate the encoded source data; and a front end to transmit the modulated and encoded source data over the communication channel.
 17. A transmitter for transmitting an encoded source data over a communication channel, comprising: a source to accept source data to be transmitted; a data input to receive source data to be encoded; a processor; and a memory to store an encoder program executable by the processor, wherein the encoder program causes the processor to encode the source data into a product coding structure, wherein the product coding structure comprises: a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, wherein the first parity block is composed of parity bits based on Bose, Chaudhuri, and Hocquenghem (BCH) coding, wherein a length of the BCH parity bits is determined such that a maximum number of correctable error bits is not less than a minimum Hamming distance for error floor reduction; a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged to cover the first parity block using the row parity block, the joint parity block and the column parity block; a modulator to modulate the encoded source data; and a front end to transmit the modulated and encoded source data over the communication channel.
 18. An encoder for encoding source data into an encoded source data to be used in a communication channel, comprising: a data input terminal to receive the source data to be encoded; a processor; and a memory to store an encoder program executable by the processor, wherein the encoder program makes the processor to encode the source data into a turbo product coding (TPC) structure, wherein the TPC structure comprises: a data block corresponding to the source data; a first parity block including a first column part, a first corner part and a first bottom part, the first parity block being arranged so as to cover a right end column of the data block, a right bottom corner of the data block and a bottom row of the data block by the first column part, the first corner part and the first bottom part, wherein the first parity block is composed of parity bits based on Bose, Chaudhuri, and Hocquenghem (BCH) coding, wherein a length of the BCH parity bits is determined such that a maximum number of correctable error bits is not less than a minimum Hamming distance for error floor reduction; and a second parity block having a row parity block, a joint parity block and a column parity block, the second parity block being arranged to cover the first parity block using the row parity block, the joint parity block and the column parity block; a front end to transmit the encoded source data over the communication channel. 